nand/raw/meson_nand.c

261 	struct meson_nfc *nfc = nand_get_controller_data(nand);
267 	nfc->param.chip_select = meson_chip->sels[chip] ? NAND_CE1 : NAND_CE0;
268 	nfc->param.rb_select = nfc->param.chip_select;
269 	nfc->timing.twb = meson_chip->twb;
270 	nfc->timing.tadl = meson_chip->tadl;
271 	nfc->timing.tbers_max = meson_chip->tbers_max;
273 	if (nfc->clk_rate != meson_chip->clk_rate) {
274 		ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate);
276 			dev_err(nfc->dev, "failed to set clock rate\n");
279 		nfc->clk_rate = meson_chip->clk_rate;
281 	if (nfc->bus_timing != meson_chip->bus_timing) {
283 		writel(value, nfc->reg_base + NFC_REG_CFG);
284 		writel((1 << 31), nfc->reg_base + NFC_REG_CMD);
285 		nfc->bus_timing =  meson_chip->bus_timing;
289 static void meson_nfc_cmd_idle(struct meson_nfc *nfc, u32 time)
291 	writel(nfc->param.chip_select | NFC_CMD_IDLE | (time & 0x3ff),
292 	       nfc->reg_base + NFC_REG_CMD);
295 static void meson_nfc_cmd_seed(struct meson_nfc *nfc, u32 seed)
298 	       nfc->reg_base + NFC_REG_CMD);
305 	struct meson_nfc *nfc = nand_get_controller_data(mtd_to_nand(mtd));
315 		writel(cmd, nfc->reg_base + NFC_REG_CMD);
324 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
327 static void meson_nfc_drain_cmd(struct meson_nfc *nfc)
340 	meson_nfc_cmd_idle(nfc, 0);
341 	meson_nfc_cmd_idle(nfc, 0);
344 static int meson_nfc_wait_cmd_finish(struct meson_nfc *nfc,
351 	ret = readl_relaxed_poll_timeout(nfc->reg_base + NFC_REG_CMD, cmd_size,
355 		dev_err(nfc->dev, "wait for empty CMD FIFO time out\n");
360 static int meson_nfc_wait_dma_finish(struct meson_nfc *nfc)
362 	meson_nfc_drain_cmd(nfc);
364 	return meson_nfc_wait_cmd_finish(nfc, DMA_BUSY_TIMEOUT);
429 	struct meson_nfc *nfc = nand_get_controller_data(nand);
432 	meson_nfc_cmd_idle(nfc, nfc->timing.twb);
433 	meson_nfc_drain_cmd(nfc);
434 	meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
436 	cfg = readl(nfc->reg_base + NFC_REG_CFG);
438 	writel(cfg, nfc->reg_base + NFC_REG_CFG);
440 	reinit_completion(&nfc->completion);
444 	cmd = NFC_CMD_RB | NFC_CMD_RB_INT_NO_PIN | nfc->timing.tbers_max;
445 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
447 	if (!wait_for_completion_timeout(&nfc->completion,
457 static int meson_nfc_wait_rb_pin(struct meson_nfc *nfc, int timeout_ms)
462 	meson_nfc_cmd_idle(nfc, nfc->timing.twb);
463 	meson_nfc_drain_cmd(nfc);
464 	meson_nfc_wait_cmd_finish(nfc, CMD_FIFO_EMPTY_TIMEOUT);
466 	cfg = readl(nfc->reg_base + NFC_REG_CFG);
468 	writel(cfg, nfc->reg_base + NFC_REG_CFG);
470 	reinit_completion(&nfc->completion);
474 		| nfc->param.chip_select | nfc->timing.tbers_max;
475 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
477 	ret = wait_for_completion_timeout(&nfc->completion,
488 	struct meson_nfc *nfc = nand_get_controller_data(nand);
490 	if (nfc->no_rb_pin) {
504 		return meson_nfc_wait_rb_pin(nfc, timeout_ms);
567 	struct meson_nfc *nfc = nand_get_controller_data(nand);
571 	nfc->daddr = dma_map_single(nfc->dev, databuf, datalen, dir);
572 	ret = dma_mapping_error(nfc->dev, nfc->daddr);
574 		dev_err(nfc->dev, "DMA mapping error\n");
577 	cmd = GENCMDDADDRL(NFC_CMD_ADL, nfc->daddr);
578 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
580 	cmd = GENCMDDADDRH(NFC_CMD_ADH, nfc->daddr);
581 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
584 		nfc->iaddr = dma_map_single(nfc->dev, infobuf, infolen, dir);
585 		ret = dma_mapping_error(nfc->dev, nfc->iaddr);
587 			dev_err(nfc->dev, "DMA mapping error\n");
588 			dma_unmap_single(nfc->dev,
589 					 nfc->daddr, datalen, dir);
592 		nfc->info_bytes = infolen;
593 		cmd = GENCMDIADDRL(NFC_CMD_AIL, nfc->iaddr);
594 		writel(cmd, nfc->reg_base + NFC_REG_CMD);
596 		cmd = GENCMDIADDRH(NFC_CMD_AIH, nfc->iaddr);
597 		writel(cmd, nfc->reg_base + NFC_REG_CMD);
607 	struct meson_nfc *nfc = nand_get_controller_data(nand);
609 	dma_unmap_single(nfc->dev, nfc->daddr, datalen, dir);
611 		dma_unmap_single(nfc->dev, nfc->iaddr, infolen, dir);
612 		nfc->info_bytes = 0;
618 	struct meson_nfc *nfc = nand_get_controller_data(nand);
633 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
635 	meson_nfc_drain_cmd(nfc);
636 	meson_nfc_wait_cmd_finish(nfc, 1000);
647 	struct meson_nfc *nfc = nand_get_controller_data(nand);
657 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
659 	meson_nfc_drain_cmd(nfc);
660 	meson_nfc_wait_cmd_finish(nfc, 1000);
672 	struct meson_nfc *nfc = nand_get_controller_data(nand);
673 	u32 *addrs = nfc->cmdfifo.rw.addrs;
674 	u32 cs = nfc->param.chip_select;
681 	nfc->cmdfifo.rw.cmd0 = cs | NFC_CMD_CLE | cmd0;
705 		writel_relaxed(nfc->cmdfifo.cmd[i],
706 			       nfc->reg_base + NFC_REG_CMD);
709 		nfc->cmdfifo.rw.cmd1 = cs | NFC_CMD_CLE | NAND_CMD_READSTART;
710 		writel(nfc->cmdfifo.rw.cmd1, nfc->reg_base + NFC_REG_CMD);
713 		meson_nfc_cmd_idle(nfc, nfc->timing.tadl);
726 	struct meson_nfc *nfc = nand_get_controller_data(nand);
747 		meson_nfc_cmd_seed(nfc, page);
755 	cmd = nfc->param.chip_select | NFC_CMD_CLE | NAND_CMD_PAGEPROG;
756 	writel(cmd, nfc->reg_base + NFC_REG_CMD);
788 static void meson_nfc_check_ecc_pages_valid(struct meson_nfc *nfc,
800 		/* info is updated by nfc dma engine*/
802 		dma_sync_single_for_cpu(nfc->dev, nfc->iaddr, nfc->info_bytes,
812 	struct meson_nfc *nfc = nand_get_controller_data(nand);
833 		meson_nfc_cmd_seed(nfc, page);
841 	ret = meson_nfc_wait_dma_finish(nfc);
842 	meson_nfc_check_ecc_pages_valid(nfc, nand, raw);
1019 	struct meson_nfc *nfc = nand_get_controller_data(nand);
1041 			cmd = nfc->param.chip_select | NFC_CMD_CLE;
1043 			writel(cmd, nfc->reg_base + NFC_REG_CMD);
1044 			meson_nfc_cmd_idle(nfc, delay_idle);
1049 				cmd = nfc->param.chip_select | NFC_CMD_ALE;
1051 				writel(cmd, nfc->reg_base + NFC_REG_CMD);
1053 			meson_nfc_cmd_idle(nfc, delay_idle);
1076 				meson_nfc_cmd_idle(nfc, delay_idle);
1080 	meson_nfc_wait_cmd_finish(nfc, 1000);
1117 static int meson_nfc_clk_init(struct meson_nfc *nfc)
1124 	nfc->core_clk = devm_clk_get(nfc->dev, "core");
1125 	if (IS_ERR(nfc->core_clk)) {
1126 		dev_err(nfc->dev, "failed to get core clock\n");
1127 		return PTR_ERR(nfc->core_clk);
1130 	nfc->device_clk = devm_clk_get(nfc->dev, "device");
1131 	if (IS_ERR(nfc->device_clk)) {
1132 		dev_err(nfc->dev, "failed to get device clock\n");
1133 		return PTR_ERR(nfc->device_clk);
1136 	init.name = devm_kasprintf(nfc->dev,
1138 				   dev_name(nfc->dev));
1146 	nfc->nand_divider.reg = nfc->reg_clk;
1147 	nfc->nand_divider.shift = CLK_DIV_SHIFT;
1148 	nfc->nand_divider.width = CLK_DIV_WIDTH;
1149 	nfc->nand_divider.hw.init = &init;
1150 	nfc->nand_divider.flags = CLK_DIVIDER_ONE_BASED |
1154 	nfc->nand_clk = devm_clk_register(nfc->dev, &nfc->nand_divider.hw);
1155 	if (IS_ERR(nfc->nand_clk))
1156 		return PTR_ERR(nfc->nand_clk);
1160 	       nfc->reg_clk);
1162 	ret = clk_prepare_enable(nfc->core_clk);
1164 		dev_err(nfc->dev, "failed to enable core clock\n");
1168 	ret = clk_prepare_enable(nfc->device_clk);
1170 		dev_err(nfc->dev, "failed to enable device clock\n");
1174 	ret = clk_prepare_enable(nfc->nand_clk);
1176 		dev_err(nfc->dev, "pre enable NFC divider fail\n");
1180 	ret = clk_set_rate(nfc->nand_clk, 24000000);
1187 	clk_disable_unprepare(nfc->nand_clk);
1189 	clk_disable_unprepare(nfc->device_clk);
1191 	clk_disable_unprepare(nfc->core_clk);
1195 static void meson_nfc_disable_clk(struct meson_nfc *nfc)
1197 	clk_disable_unprepare(nfc->nand_clk);
1198 	clk_disable_unprepare(nfc->device_clk);
1199 	clk_disable_unprepare(nfc->core_clk);
1303 	struct meson_nfc *nfc = nand_get_controller_data(nand);
1310 		mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL,
1312 					   dev_name(nfc->dev),
1320 		dev_err(nfc->dev, "too big write size in raw mode: %d > %ld\n",
1330 	ret = nand_ecc_choose_conf(nand, nfc->data->ecc_caps,
1333 		dev_err(nfc->dev, "failed to ECC init\n");
1355 		dev_err(nfc->dev, "16bits bus width not supported");
1374 			 struct meson_nfc *nfc, struct device_node *np)
1404 		if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1411 	nand->controller = &nfc->controller;
1414 	nand_set_controller_data(nand, nfc);
1423 		nfc->no_rb_pin = true;
1441 	list_add_tail(&meson_chip->node, &nfc->chips);
1446 static void meson_nfc_nand_chip_cleanup(struct meson_nfc *nfc)
1451 	while (!list_empty(&nfc->chips)) {
1452 		meson_chip = list_first_entry(&nfc->chips,
1463 				     struct meson_nfc *nfc)
1470 		ret = meson_nfc_nand_chip_init(dev, nfc, nand_np);
1472 			meson_nfc_nand_chip_cleanup(nfc);
1483 	struct meson_nfc *nfc = id;
1486 	cfg = readl(nfc->reg_base + NFC_REG_CFG);
1491 	writel(cfg, nfc->reg_base + NFC_REG_CFG);
1493 	complete(&nfc->completion);
1507 		.compatible = "amlogic,meson-gxl-nfc",
1510 		.compatible = "amlogic,meson-axg-nfc",
1520 	struct meson_nfc *nfc;
1523 	nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1524 	if (!nfc)
1527 	nfc->data = of_device_get_match_data(&pdev->dev);
1528 	if (!nfc->data)
1531 	nand_controller_init(&nfc->controller);
1532 	INIT_LIST_HEAD(&nfc->chips);
1533 	init_completion(&nfc->completion);
1535 	nfc->dev = dev;
1537 	nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc");
1538 	if (IS_ERR(nfc->reg_base))
1539 		return PTR_ERR(nfc->reg_base);
1541 	nfc->reg_clk = devm_platform_ioremap_resource_byname(pdev, "emmc");
1542 	if (IS_ERR(nfc->reg_clk))
1543 		return PTR_ERR(nfc->reg_clk);
1549 	ret = meson_nfc_clk_init(nfc);
1555 	writel(0, nfc->reg_base + NFC_REG_CFG);
1556 	ret = devm_request_irq(dev, irq, meson_nfc_irq, 0, dev_name(dev), nfc);
1569 	platform_set_drvdata(pdev, nfc);
1571 	ret = meson_nfc_nand_chips_init(dev, nfc);
1579 	meson_nfc_disable_clk(nfc);
1585 	struct meson_nfc *nfc = platform_get_drvdata(pdev);
1587 	meson_nfc_nand_chip_cleanup(nfc);
1589 	meson_nfc_disable_clk(nfc);