Lines Matching defs:sdr
1150 const struct nand_sdr_timings *sdr =
1198 PSEC_TO_MSEC(sdr->tPROG_max));
1630 const struct nand_sdr_timings *sdr =
1669 ret = marvell_nfc_wait_op(chip, PSEC_TO_MSEC(sdr->tPROG_max));
2392 const struct nand_sdr_timings *sdr;
2396 sdr = nand_get_sdr_timings(conf);
2397 if (IS_ERR(sdr))
2398 return PTR_ERR(sdr);
2414 nfc_tmg.tRP = TO_CYCLES(DIV_ROUND_UP(sdr->tRC_min, 2), period_ns) - 1;
2416 nfc_tmg.tWP = TO_CYCLES(DIV_ROUND_UP(sdr->tWC_min, 2), period_ns) - 1;
2418 nfc_tmg.tCS = TO_CYCLES(sdr->tCS_min, period_ns);
2419 nfc_tmg.tCH = TO_CYCLES(sdr->tCH_min, period_ns) - 1;
2420 nfc_tmg.tADL = TO_CYCLES(sdr->tADL_min, period_ns);
2427 read_delay = sdr->tRC_min >= 30000 ?
2430 nfc_tmg.tAR = TO_CYCLES(sdr->tAR_min, period_ns);
2436 nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),
2438 nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),
2446 nfc_tmg.tR = TO_CYCLES(sdr->tWB_max, period_ns);
2448 nfc_tmg.tR = TO_CYCLES64(sdr->tWB_max + sdr->tR_max,