nand/raw/marvell_nand.c

25  * there are at most 2 bitflips. Here is the page layout used by the
36  * 30B per ECC chunk. Here is the page layout used by the controller
51  * In both cases, the layout seen by the user is always: all data
67  *     and ECC bytes in that order, no matter what the real layout is
232  * struct marvell_hw_ecc_layout - layout of Marvell ECC
237  * a particular layout mixing data/spare/ecc is defined, with a possible last
240  * @writesize:		Full page size on which the layout applies
241  * @chunk:		Desired ECC chunk size on which the layout applies
243  *			layout applies
260 	/* Corresponding layout */
329  * @layout:		NAND layout when using hardware ECC
341 	const struct marvell_hw_ecc_layout *layout;
1040 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1098 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1154 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1260 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1310 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1375 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1469 		 * layout which is buggy in the sense that the ECC engine will
1515 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1572 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
1633 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2203 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2219 	const struct marvell_hw_ecc_layout *lt = to_marvell_nand(chip)->layout;
2260 	to_marvell_nand(chip)->layout = NULL;
2265 			to_marvell_nand(chip)->layout = l;
2270 	if (!to_marvell_nand(chip)->layout ||
2278 	/* Special care for the layout 2k/8-bit/512B  */
2281 			dev_err(nfc->dev, "Requested layout needs at least 128 OOB bytes\n");
2792 	 * properties and layout. Instead, NAND properties are mixed with the