nand/raw/marvell_nand.c

17  * The ECC layouts are depicted in details in Marvell AN-379, but here
20  * When using Hamming, the data is split in 512B chunks (either 1, 2
23  * bytes (also called "spare" bytes in the driver). This engine
61  *   - The ECC strength in BCH mode cannot be tuned. It is fixed 16
67  *     and ECC bytes in that order, no matter what the real layout is
72  *     located in data section. In this case, the NAND_BBT_NO_OOB_BBM
105 /* Interrupt maximum wait period in ms */
107 /* Latency in clock cycles between SoC pins and NFC logic */
234  * Marvell ECC engine works differently than the others, in order to limit the
251  * @last_data_bytes:	Number of data bytes in the last chunk
252  * @last_spare_bytes:	Number of spare bytes in the last chunk
253  * @last_ecc_bytes:	Number of ecc bytes in the last chunk
286 /* Layouts explained in AN-379_Marvell_SoC_NFC_ECC */
306  * is made by a field in NDCB0 register, and in another field in NDCB2 register.
430  * struct marvell_nfc_timings - NAND controller timings expressed in NAND
462  * TO_CYCLES() - Derives a duration in numbers of clock cycles.
464  * @ps: Duration in pico-seconds
465  * @period_ns:  Clock period in nano-seconds
467  * Convert the duration in nano-seconds, then divide by the period and
483  * @data_instr_idx:	Index of the data instruction in the subop
484  * @data_instr:		Pointer to the data instruction in the subop
733 	/* Timeout is expressed in ms */
752 	 * In case the interrupt was not served in the required time frame,
798 	 * RDY interrupt mask is one bit in NDCR while there are two status
799 	 * bit in NDSR (RDY[cs0/cs2] and RDY[cs1/cs3]).
912 static int marvell_nfc_xfer_data_in_pio(struct marvell_nfc *nfc, u8 *in,
920 		ioread32_rep(nfc->regs + NDDB, in + i, FIFO_REP(FIFO_DEPTH));
926 		memcpy(in + last_full_offset, tmp_buf, last_len);
1068 	 * Read the page then the OOB area. Unlike what is shown in current
1131  * Spare area in Hamming layouts is not protected by the ECC engine (even if
1238  * Spare area in Hamming layouts is not protected by the ECC engine (even if
1420 	 * the controller in normal mode and must be re-read in raw mode. To
1422 	 * user should re-read the page in raw mode if ECC bytes are required.
1427 	 * bytes in raw mode and check if the whole page is empty. In this case,
1432 	 * bits and may create itself bitflips in the erased area. To overcome
1433 	 * this strange behavior, the whole page is re-read in raw mode, not
1469 		 * layout which is buggy in the sense that the ECC engine will
1583 	 * All operations in the middle (if any) will issue a naked write and
1815 		u8 *in = instr->ctx.data.buf.in + offset;
1817 		ret = marvell_nfc_xfer_data_in_pio(nfc, in, len);
1882 	 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
1903 	 * Naked access are different in that they need to be flagged as naked
1954 	 * comes to writes (with LEN_OVRD). Clear it by hand in this case.
2196  * Layouts were broken in old pxa3xx_nand driver, these are supposed to be
2225 	 * Bootrom looks in bytes 0 & 5 for bad blocks for the
2372 	.maxblocks = 8,	/* Last 8 blocks in each chip */
2382 	.maxblocks = 8,	/* Last 8 blocks in each chip */
2404 	 * SDR timings are given in pico-seconds while NFC timings must be
2405 	 * expressed in NAND controller clock cycles, which is half of the
2407 	 * This is not written anywhere in the datasheet but was observed
2433 	 * versa) but in some cases, ie. when doing a change column, they must
2486 	 * registers to be updated in marvell_nfc_select_target().
2506 		 * We'll use a bad block table stored in-flash and don't
2535 	 * cycle but due to inconsistance in the documentation and lack of
2557 		 * subpage read as in userspace subpage access would still be
2575 		 * should define the following property in your NAND node, ie:
2644 			 * Legacy bindings use the CS lines in natural
2671 		 * converted in bit fields for NDCB0 and NDCB2 to select the
2674 		 * use CS1 and CS3 at all as asserting them is not supported in
2828 			 "DMA not enabled in configuration\n");
2888 	 * needed. ECC shall not be activated in the early stages (fails probe).
2891 	 * offset in the read page and this will fail the protection.
3079 	 * registers to be restored in marvell_nfc_select_target().