nand/raw/marvell_nand.c

237  * a particular layout mixing data/spare/ecc is defined, with a possible last
250  * @ecc_bytes:		Number of ecc bytes per chunk
253  * @last_ecc_bytes:	Number of ecc bytes in the last chunk
828 		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
840 		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
955 					  u8 *ecc, int ecc_len,
970 	if (!ecc)
973 	bf = nand_check_erased_ecc_chunk(data, data_len, ecc, ecc_len,
974 					 spare, spare_len, chip->ecc.strength);
1020 		if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
1486 		/* Check the entire chunk (data + spare + ecc) for emptyness */
1500 	return chip->ecc.read_page_raw(chip, buf, true, page);
1507 	return chip->ecc.read_page(chip, buf, true, page);
1695 	return chip->ecc.write_page_raw(chip, buf, true, page);
1705 	return chip->ecc.write_page(chip, buf, true, page);
2240 	.ecc = marvell_nand_ooblayout_ecc,
2245 					       struct nand_ecc_ctrl *ecc)
2264 		    ecc->size == l->chunk && ecc->strength == l->strength) {
2271 	    (!nfc->caps->is_nfcv2 && ecc->strength > 1)) {
2274 			ecc->strength, mtd->writesize);
2289 	ecc->steps = l->nchunks;
2290 	ecc->size = l->data_bytes;
2292 	if (ecc->strength == 1) {
2293 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
2294 		ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
2295 		ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
2296 		ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
2297 		ecc->read_oob = ecc->read_oob_raw;
2298 		ecc->write_page_raw = marvell_nfc_hw_ecc_hmg_write_page_raw;
2299 		ecc->write_page = marvell_nfc_hw_ecc_hmg_write_page;
2300 		ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
2301 		ecc->write_oob = ecc->write_oob_raw;
2303 		chip->ecc.algo = NAND_ECC_ALGO_BCH;
2304 		ecc->strength = 16;
2305 		ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
2306 		ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
2307 		ecc->read_oob_raw = marvell_nfc_hw_ecc_bch_read_oob_raw;
2308 		ecc->read_oob = marvell_nfc_hw_ecc_bch_read_oob;
2309 		ecc->write_page_raw = marvell_nfc_hw_ecc_bch_write_page_raw;
2310 		ecc->write_page = marvell_nfc_hw_ecc_bch_write_page;
2311 		ecc->write_oob_raw = marvell_nfc_hw_ecc_bch_write_oob_raw;
2312 		ecc->write_oob = marvell_nfc_hw_ecc_bch_write_oob;
2319 				 struct nand_ecc_ctrl *ecc)
2327 	if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE &&
2328 	    (!ecc->size || !ecc->strength)) {
2330 			ecc->size = requirements->step_size;
2331 			ecc->strength = requirements->strength;
2335 			ecc->size = 512;
2336 			ecc->strength = 1;
2340 	switch (ecc->engine_type) {
2342 		ret = marvell_nand_hw_ecc_controller_init(mtd, ecc);
2544 		chip->ecc.size = pdata->ecc_step_size;
2545 		chip->ecc.strength = pdata->ecc_strength;
2548 	ret = marvell_nand_ecc_init(mtd, &chip->ecc);
2554 	if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {