nand/raw/lpc32xx_mlc.c

231 static void lpc32xx_nand_setup(struct lpc32xx_nand_host *host)
236 	writel(MLCCMD_RESET, MLC_CMD(host->io_base));
240 	clkrate = clk_get_rate(host->clk);
246 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
250 	writel(tmp, MLC_ICR(host->io_base));
254 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
258 	tmp |= MLCTIMEREG_TCEA_DELAY(clkrate / host->ncfg->tcea_delay + 1);
259 	tmp |= MLCTIMEREG_BUSY_DELAY(clkrate / host->ncfg->busy_delay + 1);
260 	tmp |= MLCTIMEREG_NAND_TA(clkrate / host->ncfg->nand_ta + 1);
261 	tmp |= MLCTIMEREG_RD_HIGH(clkrate / host->ncfg->rd_high + 1);
262 	tmp |= MLCTIMEREG_RD_LOW(clkrate / host->ncfg->rd_low);
263 	tmp |= MLCTIMEREG_WR_HIGH(clkrate / host->ncfg->wr_high + 1);
264 	tmp |= MLCTIMEREG_WR_LOW(clkrate / host->ncfg->wr_low);
265 	writel(tmp, MLC_TIME_REG(host->io_base));
269 			MLC_IRQ_MR(host->io_base));
272 	writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
281 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
285 			writel(cmd, MLC_CMD(host->io_base));
287 			writel(cmd, MLC_ADDR(host->io_base));
296 	struct lpc32xx_nand_host *host = nand_get_controller_data(nand_chip);
298 	if ((readb(MLC_ISR(host->io_base)) &
308 	struct lpc32xx_nand_host *host = data;
312 	sr = readb(MLC_IRQ_SR(host->io_base));
314 		complete(&host->comp_nand);
316 		complete(&host->comp_controller);
324 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
326 	if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
329 	wait_for_completion(&host->comp_nand);
331 	while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
344 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
346 	if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
349 	wait_for_completion(&host->comp_controller);
351 	while (!(readb(MLC_ISR(host->io_base)) &
372 static void lpc32xx_wp_enable(struct lpc32xx_nand_host *host)
374 	if (host->wp_gpio)
375 		gpiod_set_value_cansleep(host->wp_gpio, 1);
381 static void lpc32xx_wp_disable(struct lpc32xx_nand_host *host)
383 	if (host->wp_gpio)
384 		gpiod_set_value_cansleep(host->wp_gpio, 0);
396 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
401 	sg_init_one(&host->sgl, mem, len);
403 	res = dma_map_sg(host->dma_chan->device->dev, &host->sgl, 1,
409 	desc = dmaengine_prep_slave_sg(host->dma_chan, &host->sgl, 1, dir,
416 	init_completion(&host->comp_dma);
418 	desc->callback_param = &host->comp_dma;
421 	dma_async_issue_pending(host->dma_chan);
423 	wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
425 	dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
429 	dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
438 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
450 		dma_buf = host->dma_buf;
458 	for (i = 0; i < host->mlcsubpages; i++) {
460 		writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
466 		mlc_isr = readl(MLC_ISR(host->io_base));
483 					readl(MLC_BUFF(host->io_base));
489 				readl(MLC_BUFF(host->io_base));
505 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
512 		dma_buf = host->dma_buf;
518 	for (i = 0; i < host->mlcsubpages; i++) {
520 		writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
531 				       MLC_BUFF(host->io_base));
535 		writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
537 		writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
541 		writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
552 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
555 	lpc32xx_read_page(chip, host->dummy_buf, 1, page);
572 static int lpc32xx_dma_setup(struct lpc32xx_nand_host *host)
574 	struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
577 	if (!host->pdata || !host->pdata->dma_filter) {
584 	host->dma_chan = dma_request_channel(mask, host->pdata->dma_filter,
586 	if (!host->dma_chan) {
596 	host->dma_slave_config.direction = DMA_DEV_TO_MEM;
597 	host->dma_slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
598 	host->dma_slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 	host->dma_slave_config.src_maxburst = 128;
600 	host->dma_slave_config.dst_maxburst = 128;
602 	host->dma_slave_config.device_fc = false;
603 	host->dma_slave_config.src_addr = MLC_BUFF(host->io_base_phy);
604 	host->dma_slave_config.dst_addr = MLC_BUFF(host->io_base_phy);
605 	if (dmaengine_slave_config(host->dma_chan, &host->dma_slave_config)) {
612 	dma_release_channel(host->dma_chan);
646 	struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
647 	struct device *dev = &host->pdev->dev;
652 	host->dma_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
653 	if (!host->dma_buf)
656 	host->dummy_buf = devm_kzalloc(dev, mtd->writesize, GFP_KERNEL);
657 	if (!host->dummy_buf)
672 	host->mlcsubpages = mtd->writesize / 512;
686 	struct lpc32xx_nand_host *host;
693 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
694 	if (!host)
697 	host->pdev = pdev;
699 	host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);
700 	if (IS_ERR(host->io_base))
701 		return PTR_ERR(host->io_base);
703 	host->io_base_phy = rc->start;
705 	nand_chip = &host->nand_chip;
708 		host->ncfg = lpc32xx_parse_dt(&pdev->dev);
709 	if (!host->ncfg) {
716 	host->wp_gpio = gpiod_get_optional(&pdev->dev, NULL, GPIOD_OUT_LOW);
717 	res = PTR_ERR_OR_ZERO(host->wp_gpio);
725 	gpiod_set_consumer_name(host->wp_gpio, "NAND WP");
727 	host->pdata = dev_get_platdata(&pdev->dev);
730 	nand_set_controller_data(nand_chip, host);
735 	host->clk = clk_get(&pdev->dev, NULL);
736 	if (IS_ERR(host->clk)) {
741 	res = clk_prepare_enable(host->clk);
748 	nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
749 	nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
752 	lpc32xx_nand_setup(host);
754 	platform_set_drvdata(pdev, host);
765 		res = lpc32xx_dma_setup(host);
773 	readb(MLC_IRQ_SR(host->io_base));
775 	init_completion(&host->comp_nand);
776 	init_completion(&host->comp_controller);
778 	host->irq = platform_get_irq(pdev, 0);
779 	if (host->irq < 0) {
784 	if (request_irq(host->irq, &lpc3xxx_nand_irq,
785 			IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
802 	res = mtd_device_register(mtd, host->ncfg->parts,
803 				  host->ncfg->num_parts);
812 	free_irq(host->irq, host);
815 		dma_release_channel(host->dma_chan);
817 	clk_disable_unprepare(host->clk);
819 	clk_put(host->clk);
821 	lpc32xx_wp_enable(host);
822 	gpiod_put(host->wp_gpio);
832 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
833 	struct nand_chip *chip = &host->nand_chip;
840 	free_irq(host->irq, host);
842 		dma_release_channel(host->dma_chan);
844 	clk_disable_unprepare(host->clk);
845 	clk_put(host->clk);
847 	lpc32xx_wp_enable(host);
848 	gpiod_put(host->wp_gpio);
853 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
857 	ret = clk_prepare_enable(host->clk);
862 	lpc32xx_nand_setup(host);
865 	lpc32xx_wp_disable(host);
872 	struct lpc32xx_nand_host *host = platform_get_drvdata(pdev);
875 	lpc32xx_wp_enable(host);
878 	clk_disable_unprepare(host->clk);