Lines Matching defs:ecc
18 #include <linux/mtd/nand-ecc-mtk.h>
71 /* ecc strength that each IP supports */
126 static inline void mtk_ecc_wait_idle(struct mtk_ecc *ecc,
129 struct device *dev = ecc->dev;
133 ret = readl_poll_timeout_atomic(ecc->regs + ECC_IDLE_REG(op), val,
143 struct mtk_ecc *ecc = id;
146 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA])
149 dec = readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
150 if (dec & ecc->sectors) {
155 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_STA]);
156 ecc->sectors = 0;
157 complete(&ecc->done);
162 enc = readl(ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_STA])
165 complete(&ecc->done);
173 static int mtk_ecc_config(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
178 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
179 if (ecc->caps->ecc_strength[i] == config->strength)
183 if (i == ecc->caps->num_ecc_strength) {
184 dev_err(ecc->dev, "invalid ecc strength %d\n",
195 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
197 writel(reg, ecc->regs + ECC_ENCCNFG);
201 ecc->regs + ECC_ENCDIADDR);
206 config->strength * ecc->caps->parity_bits;
208 reg = ecc_bit | (config->mode << ecc->caps->ecc_mode_shift);
211 writel(reg, ecc->regs + ECC_DECCNFG);
214 ecc->sectors = 1 << (config->sectors - 1);
220 void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats,
231 err = readl(ecc->regs + ECC_DECENUM0 + offset);
232 err = err >> ((i % 4) * ecc->caps->err_shift);
233 err &= ecc->caps->err_mask;
234 if (err == ecc->caps->err_mask) {
248 void mtk_ecc_release(struct mtk_ecc *ecc)
250 clk_disable_unprepare(ecc->clk);
251 put_device(ecc->dev);
255 static void mtk_ecc_hw_init(struct mtk_ecc *ecc)
257 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
258 writew(ECC_OP_DISABLE, ecc->regs + ECC_ENCCON);
260 mtk_ecc_wait_idle(ecc, ECC_DECODE);
261 writel(ECC_OP_DISABLE, ecc->regs + ECC_DECCON);
267 struct mtk_ecc *ecc;
273 ecc = platform_get_drvdata(pdev);
274 if (!ecc) {
279 clk_prepare_enable(ecc->clk);
280 mtk_ecc_hw_init(ecc);
282 return ecc;
287 struct mtk_ecc *ecc = NULL;
290 np = of_parse_phandle(of_node, "nand-ecc-engine", 0);
293 np = of_parse_phandle(of_node, "ecc-engine", 0);
295 ecc = mtk_ecc_get(np);
299 return ecc;
303 int mtk_ecc_enable(struct mtk_ecc *ecc, struct mtk_ecc_config *config)
309 ret = mutex_lock_interruptible(&ecc->lock);
311 dev_err(ecc->dev, "interrupted when attempting to lock\n");
315 mtk_ecc_wait_idle(ecc, op);
317 ret = mtk_ecc_config(ecc, config);
319 mutex_unlock(&ecc->lock);
324 init_completion(&ecc->done);
327 * For ECC_NFI_MODE, if ecc->caps->pg_irq_sel is 1, then it
328 * means this chip can only generate one ecc irq during page
329 * read / write. If is 0, generate one ecc irq each ecc step.
331 if (ecc->caps->pg_irq_sel && config->mode == ECC_NFI_MODE)
334 writew(reg_val, ecc->regs +
335 ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
337 writew(reg_val, ecc->regs +
338 ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
341 writew(ECC_OP_ENABLE, ecc->regs + ECC_CTL_REG(op));
347 void mtk_ecc_disable(struct mtk_ecc *ecc)
352 if (readw(ecc->regs + ECC_CTL_REG(op)) != ECC_OP_ENABLE)
356 mtk_ecc_wait_idle(ecc, op);
362 readw(ecc->regs + ecc->caps->ecc_regs[ECC_DECDONE]);
363 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_DECIRQ_EN]);
365 writew(0, ecc->regs + ecc->caps->ecc_regs[ECC_ENCIRQ_EN]);
368 writew(ECC_OP_DISABLE, ecc->regs + ECC_CTL_REG(op));
370 mutex_unlock(&ecc->lock);
374 int mtk_ecc_wait_done(struct mtk_ecc *ecc, enum mtk_ecc_operation op)
378 ret = wait_for_completion_timeout(&ecc->done, msecs_to_jiffies(500));
380 dev_err(ecc->dev, "%s timeout - interrupt did not arrive)\n",
389 int mtk_ecc_encode(struct mtk_ecc *ecc, struct mtk_ecc_config *config,
396 addr = dma_map_single(ecc->dev, data, bytes, DMA_TO_DEVICE);
397 ret = dma_mapping_error(ecc->dev, addr);
399 dev_err(ecc->dev, "dma mapping error\n");
405 ret = mtk_ecc_enable(ecc, config);
407 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
411 ret = mtk_ecc_wait_done(ecc, ECC_ENCODE);
415 mtk_ecc_wait_idle(ecc, ECC_ENCODE);
418 len = (config->strength * ecc->caps->parity_bits + 7) >> 3;
421 __ioread32_copy(ecc->eccdata,
422 ecc->regs + ecc->caps->ecc_regs[ECC_ENCPAR00],
426 memcpy(data + bytes, ecc->eccdata, len);
429 dma_unmap_single(ecc->dev, addr, bytes, DMA_TO_DEVICE);
430 mtk_ecc_disable(ecc);
436 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p)
438 const u8 *ecc_strength = ecc->caps->ecc_strength;
441 for (i = 0; i < ecc->caps->num_ecc_strength; i++) {
451 *p = ecc_strength[ecc->caps->num_ecc_strength - 1];
455 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc)
457 return ecc->caps->parity_bits;
507 .compatible = "mediatek,mt2701-ecc",
510 .compatible = "mediatek,mt2712-ecc",
513 .compatible = "mediatek,mt7622-ecc",
516 .compatible = "mediatek,mt7986-ecc",
525 struct mtk_ecc *ecc;
529 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
530 if (!ecc)
533 ecc->caps = of_device_get_match_data(dev);
535 max_eccdata_size = ecc->caps->num_ecc_strength - 1;
536 max_eccdata_size = ecc->caps->ecc_strength[max_eccdata_size];
537 max_eccdata_size = (max_eccdata_size * ecc->caps->parity_bits + 7) >> 3;
539 ecc->eccdata = devm_kzalloc(dev, max_eccdata_size, GFP_KERNEL);
540 if (!ecc->eccdata)
543 ecc->regs = devm_platform_ioremap_resource(pdev, 0);
544 if (IS_ERR(ecc->regs))
545 return PTR_ERR(ecc->regs);
547 ecc->clk = devm_clk_get(dev, NULL);
548 if (IS_ERR(ecc->clk)) {
549 dev_err(dev, "failed to get clock: %ld\n", PTR_ERR(ecc->clk));
550 return PTR_ERR(ecc->clk);
563 ret = devm_request_irq(dev, irq, mtk_ecc_irq, 0x0, "mtk-ecc", ecc);
569 ecc->dev = dev;
570 mutex_init(&ecc->lock);
571 platform_set_drvdata(pdev, ecc);
580 struct mtk_ecc *ecc = dev_get_drvdata(dev);
582 clk_disable_unprepare(ecc->clk);
589 struct mtk_ecc *ecc = dev_get_drvdata(dev);
592 ret = clk_prepare_enable(ecc->clk);
609 .name = "mtk-ecc",