Lines Matching refs:bus_width
72 * &bus_width: memory bus-width (eg: x16 2 Bytes, x32 4 Bytes)
76 int bus_width;
94 static inline u_int build_mr_cfgmask(u_int bus_width)
98 if (bus_width == 0x0004) /* x32 device */
107 static inline u_int build_sr_ok_datamask(u_int bus_width)
111 if (bus_width == 0x0004) /* x32 device */
125 val = map->pfow_base + offset*pcm_data->bus_width;
140 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
155 writel_relaxed(build_mr_cfgmask(pcm_data->bus_width) | 0x18,
172 u_int sr_ok_datamask = build_sr_ok_datamask(pcm_data->bus_width);
191 if (pcm_data->bus_width == 0x0004) { /* 2x16 devices stacked */
213 if (pcm_data->bus_width == 0x0004) /* 2x16 devices stacked */
220 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices stacked */
338 if (pcm_data->bus_width == 0x0004) {/* 2x16 devices */
347 add += pcm_data->bus_width;
348 tot_len += pcm_data->bus_width;
422 pcm_data->bus_width = BUS_WIDTH;
444 .bankwidth = pcm_data->bus_width / 2,
464 mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width;
465 mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width;