mmc/host/wmt-sdmmc.c

212 	u32 reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
215 		reg_tmp &= ~BM_SD_OFF;
217 		reg_tmp |= BM_SD_OFF;
219 	writeb(reg_tmp, priv->sdmmc_base + SDMMC_BUSMODE);
247 	u32 reg_tmp;
249 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
250 	writeb(reg_tmp | CTLR_CMD_START, priv->sdmmc_base + SDMMC_CTLR);
257 	u32 reg_tmp;
267 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
268 	writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
280 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
281 	writeb((reg_tmp & 0x0F) | (cmdtype << 4),
375 	u32 reg_tmp;
385 	reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
386 	if ((reg_tmp & INT0_DI_INT_EN) && (status0 & STS0_DEVICE_INS)) {
464 	u32 reg_tmp;
469 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
470 	writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
473 	reg_tmp = readb(priv->sdmmc_base + SDMMC_CTLR);
474 	writeb(reg_tmp | CTLR_FIFO_RESET, priv->sdmmc_base + SDMMC_CTLR);
493 	reg_tmp = readb(priv->sdmmc_base + SDMMC_STS2);
494 	writeb(reg_tmp | STS2_DIS_FORCECLK, priv->sdmmc_base + SDMMC_STS2);
527 	u32 reg_tmp;
540 		reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
541 		writel(reg_tmp & DMA_CCR_IF_TO_PERIPHERAL, priv->sdmmc_base +
544 		reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
545 		writel(reg_tmp | DMA_CCR_PERIPHERAL_TO_IF, priv->sdmmc_base +
552 	u32 reg_tmp;
554 	reg_tmp = readl(priv->sdmmc_base + SDDMA_CCR);
555 	writel(reg_tmp | DMA_CCR_RUN, priv->sdmmc_base + SDDMA_CCR);
566 	u32 reg_tmp;
609 		reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
610 		writew((reg_tmp & 0xF800) | (req->data->blksz - 1),
886 	u32 reg_tmp;
892 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
893 	writel(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base + SDMMC_BUSMODE);
894 	reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
895 	writew(reg_tmp & ~(0xA000), priv->sdmmc_base + SDMMC_BLKLEN);
921 	u32 reg_tmp;
929 	reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
930 	writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
933 	reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
934 	writew(reg_tmp & 0x5FFF, priv->sdmmc_base + SDMMC_BLKLEN);
945 	u32 reg_tmp;
953 		reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
954 		writeb(reg_tmp | BM_SOFT_RESET, priv->sdmmc_base +
957 		reg_tmp = readw(priv->sdmmc_base + SDMMC_BLKLEN);
958 		writew(reg_tmp | (BLKL_GPI_CD | BLKL_INT_ENABLE),
961 		reg_tmp = readb(priv->sdmmc_base + SDMMC_INTMASK0);
962 		writeb(reg_tmp | INT0_DI_INT_EN, priv->sdmmc_base +