Lines Matching refs:host
3 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
30 #include <linux/mmc/host.h>
40 pr_debug("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
43 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
50 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
52 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd);
54 void sdhci_dumpregs(struct sdhci_host *host)
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
83 sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
92 sdhci_readl(host, SDHCI_RESPONSE),
93 sdhci_readl(host, SDHCI_RESPONSE + 4));
95 sdhci_readl(host, SDHCI_RESPONSE + 8),
96 sdhci_readl(host, SDHCI_RESPONSE + 12));
98 sdhci_readw(host, SDHCI_HOST_CONTROL2));
100 if (host->flags & SDHCI_USE_ADMA) {
101 if (host->flags & SDHCI_USE_64_BIT_DMA) {
103 sdhci_readl(host, SDHCI_ADMA_ERROR),
104 sdhci_readl(host, SDHCI_ADMA_ADDRESS_HI),
105 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
108 sdhci_readl(host, SDHCI_ADMA_ERROR),
109 sdhci_readl(host, SDHCI_ADMA_ADDRESS));
113 if (host->ops->dump_vendor_regs)
114 host->ops->dump_vendor_regs(host);
126 static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
139 * This can be called before sdhci_add_host() by Vendor's host controller
142 void sdhci_enable_v4_mode(struct sdhci_host *host)
144 host->v4_mode = true;
145 sdhci_do_enable_v4_mode(host);
154 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
158 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
159 !mmc_card_is_removable(host->mmc) || mmc_can_gpio_cd(host->mmc))
163 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
166 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
169 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
172 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
173 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
176 static void sdhci_enable_card_detection(struct sdhci_host *host)
178 sdhci_set_card_detection(host, true);
181 static void sdhci_disable_card_detection(struct sdhci_host *host)
183 sdhci_set_card_detection(host, false);
186 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
188 if (host->bus_on)
190 host->bus_on = true;
191 pm_runtime_get_noresume(mmc_dev(host->mmc));
194 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
196 if (!host->bus_on)
198 host->bus_on = false;
199 pm_runtime_put_noidle(mmc_dev(host->mmc));
202 void sdhci_reset(struct sdhci_host *host, u8 mask)
206 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
209 host->clock = 0;
211 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
212 sdhci_runtime_pm_bus_off(host);
222 if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
226 mmc_hostname(host->mmc), (int)mask);
227 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
228 sdhci_dumpregs(host);
236 static bool sdhci_do_reset(struct sdhci_host *host, u8 mask)
238 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
239 struct mmc_host *mmc = host->mmc;
245 host->ops->reset(host, mask);
250 static void sdhci_reset_for_all(struct sdhci_host *host)
252 if (sdhci_do_reset(host, SDHCI_RESET_ALL)) {
253 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
254 if (host->ops->enable_dma)
255 host->ops->enable_dma(host);
258 host->preset_enabled = false;
271 static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
273 if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) {
274 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
280 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
286 sdhci_do_reset(host, SDHCI_RESET_CMD);
287 sdhci_do_reset(host, SDHCI_RESET_DATA);
290 sdhci_do_reset(host, SDHCI_RESET_DATA);
297 static void sdhci_set_default_irqs(struct sdhci_host *host)
299 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
305 if (host->tuning_mode == SDHCI_TUNING_MODE_2 ||
306 host->tuning_mode == SDHCI_TUNING_MODE_3)
307 host->ier |= SDHCI_INT_RETUNE;
309 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
310 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
313 static void sdhci_config_dma(struct sdhci_host *host)
318 if (host->version < SDHCI_SPEC_200)
321 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
329 if (!(host->flags & SDHCI_REQ_USE_DMA))
333 if (host->flags & SDHCI_USE_ADMA)
336 if (host->flags & SDHCI_USE_64_BIT_DMA) {
342 if (host->v4_mode) {
343 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
345 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
346 } else if (host->flags & SDHCI_USE_ADMA) {
356 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
359 static void sdhci_init(struct sdhci_host *host, int soft)
361 struct mmc_host *mmc = host->mmc;
365 sdhci_reset_for(host, INIT);
367 sdhci_reset_for_all(host);
369 if (host->v4_mode)
370 sdhci_do_enable_v4_mode(host);
372 spin_lock_irqsave(&host->lock, flags);
373 sdhci_set_default_irqs(host);
374 spin_unlock_irqrestore(&host->lock, flags);
376 host->cqe_on = false;
380 host->clock = 0;
381 host->reinit_uhs = true;
386 static void sdhci_reinit(struct sdhci_host *host)
388 u32 cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
390 sdhci_init(host, 0);
391 sdhci_enable_card_detection(host);
396 * been missed while the host controller was being reset, so trigger a
399 if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
400 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
403 static void __sdhci_led_activate(struct sdhci_host *host)
407 if (host->quirks & SDHCI_QUIRK_NO_LED)
410 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
415 static void __sdhci_led_deactivate(struct sdhci_host *host)
419 if (host->quirks & SDHCI_QUIRK_NO_LED)
422 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
424 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
431 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
434 spin_lock_irqsave(&host->lock, flags);
436 if (host->runtime_suspended)
440 __sdhci_led_deactivate(host);
442 __sdhci_led_activate(host);
444 spin_unlock_irqrestore(&host->lock, flags);
447 static int sdhci_led_register(struct sdhci_host *host)
449 struct mmc_host *mmc = host->mmc;
451 if (host->quirks & SDHCI_QUIRK_NO_LED)
454 snprintf(host->led_name, sizeof(host->led_name),
457 host->led.name = host->led_name;
458 host->led.brightness = LED_OFF;
459 host->led.default_trigger = mmc_hostname(mmc);
460 host->led.brightness_set = sdhci_led_control;
462 return led_classdev_register(mmc_dev(mmc), &host->led);
465 static void sdhci_led_unregister(struct sdhci_host *host)
467 if (host->quirks & SDHCI_QUIRK_NO_LED)
470 led_classdev_unregister(&host->led);
473 static inline void sdhci_led_activate(struct sdhci_host *host)
477 static inline void sdhci_led_deactivate(struct sdhci_host *host)
483 static inline int sdhci_led_register(struct sdhci_host *host)
488 static inline void sdhci_led_unregister(struct sdhci_host *host)
492 static inline void sdhci_led_activate(struct sdhci_host *host)
494 __sdhci_led_activate(host);
497 static inline void sdhci_led_deactivate(struct sdhci_host *host)
499 __sdhci_led_deactivate(host);
504 static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq,
508 mod_timer(&host->data_timer, timeout);
510 mod_timer(&host->timer, timeout);
513 static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq)
516 del_timer(&host->data_timer);
518 del_timer(&host->timer);
521 static inline bool sdhci_has_requests(struct sdhci_host *host)
523 return host->cmd || host->data_cmd;
532 static void sdhci_read_block_pio(struct sdhci_host *host)
540 blksize = host->data->blksz;
544 BUG_ON(!sg_miter_next(&host->sg_miter));
546 len = min(host->sg_miter.length, blksize);
549 host->sg_miter.consumed = len;
551 buf = host->sg_miter.addr;
555 scratch = sdhci_readl(host, SDHCI_BUFFER);
568 sg_miter_stop(&host->sg_miter);
571 static void sdhci_write_block_pio(struct sdhci_host *host)
579 blksize = host->data->blksz;
584 BUG_ON(!sg_miter_next(&host->sg_miter));
586 len = min(host->sg_miter.length, blksize);
589 host->sg_miter.consumed = len;
591 buf = host->sg_miter.addr;
601 sdhci_writel(host, scratch, SDHCI_BUFFER);
608 sg_miter_stop(&host->sg_miter);
611 static void sdhci_transfer_pio(struct sdhci_host *host)
615 if (host->blocks == 0)
618 if (host->data->flags & MMC_DATA_READ)
628 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
629 (host->data->blocks == 1))
632 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
633 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
636 if (host->data->flags & MMC_DATA_READ)
637 sdhci_read_block_pio(host);
639 sdhci_write_block_pio(host);
641 host->blocks--;
642 if (host->blocks == 0)
649 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
662 if (host->bounce_buffer) {
665 if (length > host->bounce_buffer_size) {
667 mmc_hostname(host->mmc), length,
668 host->bounce_buffer_size);
673 if (host->ops->copy_to_bounce_buffer) {
674 host->ops->copy_to_bounce_buffer(host,
678 host->bounce_buffer, length);
682 dma_sync_single_for_device(mmc_dev(host->mmc),
683 host->bounce_addr,
684 host->bounce_buffer_size,
690 sg_count = dma_map_sg(mmc_dev(host->mmc),
714 void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
724 if (host->flags & SDHCI_USE_64_BIT_DMA)
727 *desc += host->desc_sz;
731 static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
735 if (host->ops->adma_write_desc)
736 host->ops->adma_write_desc(host, desc, addr, len, cmd);
738 sdhci_adma_write_desc(host, desc, addr, len, cmd);
749 static void sdhci_adma_table_pre(struct sdhci_host *host,
763 host->sg_count = sg_count;
765 desc = host->adma_table;
766 align = host->align_buffer;
768 align_addr = host->align_addr;
770 for_each_sg(data->sg, sg, host->sg_count, i) {
790 __sdhci_adma_write_desc(host, &desc, align_addr,
808 while (len > host->max_adma) {
811 __sdhci_adma_write_desc(host, &desc, addr, n, ADMA2_TRAN_VALID);
818 __sdhci_adma_write_desc(host, &desc, addr, len,
825 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
828 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
830 if (desc != host->adma_table) {
831 desc -= host->desc_sz;
836 __sdhci_adma_write_desc(host, &desc, 0, 0, ADMA2_NOP_END_VALID);
840 static void sdhci_adma_table_post(struct sdhci_host *host,
852 for_each_sg(data->sg, sg, host->sg_count, i)
859 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
862 align = host->align_buffer;
864 for_each_sg(data->sg, sg, host->sg_count, i) {
880 static void sdhci_set_adma_addr(struct sdhci_host *host, dma_addr_t addr)
882 sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
883 if (host->flags & SDHCI_USE_64_BIT_DMA)
884 sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
887 static dma_addr_t sdhci_sdma_address(struct sdhci_host *host)
889 if (host->bounce_buffer)
890 return host->bounce_addr;
892 return sg_dma_address(host->data->sg);
895 static void sdhci_set_sdma_addr(struct sdhci_host *host, dma_addr_t addr)
897 if (host->v4_mode)
898 sdhci_set_adma_addr(host, addr);
900 sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
903 static unsigned int sdhci_target_timeout(struct sdhci_host *host,
914 if (host->clock && data->timeout_clks) {
919 * host->clock is in Hz. target_timeout is in us.
923 if (do_div(val, host->clock))
932 static void sdhci_calc_sw_timeout(struct sdhci_host *host,
936 struct mmc_host *mmc = host->mmc;
944 target_timeout = sdhci_target_timeout(host, cmd, data);
949 freq = mmc->actual_clock ? : host->clock;
955 host->data_timeout = data->blocks * target_timeout +
958 host->data_timeout = target_timeout;
961 if (host->data_timeout)
962 host->data_timeout += MMC_CMD_TRANSFER_TIME;
965 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd,
975 * If the host controller provides us with an incorrect timeout
980 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
981 return host->max_timeout_count;
985 return host->max_timeout_count;
990 return host->max_timeout_count;
993 target_timeout = sdhci_target_timeout(host, cmd, data);
1001 * (2) host->timeout_clk < 2^16
1006 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
1010 if (count > host->max_timeout_count) {
1011 if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
1014 count = host->max_timeout_count;
1023 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
1028 if (host->flags & SDHCI_REQ_USE_DMA)
1029 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
1031 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
1033 if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
1034 host->ier |= SDHCI_INT_AUTO_CMD_ERR;
1036 host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
1038 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1039 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1042 void sdhci_set_data_timeout_irq(struct sdhci_host *host, bool enable)
1045 host->ier |= SDHCI_INT_DATA_TIMEOUT;
1047 host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
1048 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1049 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1053 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1056 u8 count = sdhci_calc_timeout(host, cmd, &too_big);
1059 host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT) {
1060 sdhci_calc_sw_timeout(host, cmd);
1061 sdhci_set_data_timeout_irq(host, false);
1062 } else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT)) {
1063 sdhci_set_data_timeout_irq(host, true);
1066 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
1070 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
1072 if (host->ops->set_timeout)
1073 host->ops->set_timeout(host, cmd);
1075 __sdhci_set_timeout(host, cmd);
1078 static void sdhci_initialize_data(struct sdhci_host *host,
1081 WARN_ON(host->data);
1085 BUG_ON(data->blksz > host->mmc->max_blk_size);
1088 host->data = data;
1089 host->data_early = 0;
1090 host->data->bytes_xfered = 0;
1093 static inline void sdhci_set_block_info(struct sdhci_host *host,
1097 sdhci_writew(host,
1098 SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz),
1104 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1105 (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) {
1106 if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
1107 sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
1108 sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT);
1110 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
1114 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
1118 sdhci_initialize_data(host, data);
1120 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1125 host->flags |= SDHCI_REQ_USE_DMA;
1136 if (host->flags & SDHCI_USE_ADMA) {
1137 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
1147 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
1149 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
1158 host->flags &= ~SDHCI_REQ_USE_DMA;
1163 host->flags &= ~SDHCI_REQ_USE_DMA;
1170 sdhci_config_dma(host);
1172 if (host->flags & SDHCI_REQ_USE_DMA) {
1173 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1181 host->flags &= ~SDHCI_REQ_USE_DMA;
1182 } else if (host->flags & SDHCI_USE_ADMA) {
1183 sdhci_adma_table_pre(host, data, sg_cnt);
1184 sdhci_set_adma_addr(host, host->adma_addr);
1187 sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
1191 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
1195 if (host->data->flags & MMC_DATA_READ)
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1200 host->blocks = data->blocks;
1203 sdhci_set_transfer_irqs(host);
1205 sdhci_set_block_info(host, data);
1210 static int sdhci_external_dma_init(struct sdhci_host *host)
1213 struct mmc_host *mmc = host->mmc;
1215 host->tx_chan = dma_request_chan(mmc_dev(mmc), "tx");
1216 if (IS_ERR(host->tx_chan)) {
1217 ret = PTR_ERR(host->tx_chan);
1220 host->tx_chan = NULL;
1224 host->rx_chan = dma_request_chan(mmc_dev(mmc), "rx");
1225 if (IS_ERR(host->rx_chan)) {
1226 if (host->tx_chan) {
1227 dma_release_channel(host->tx_chan);
1228 host->tx_chan = NULL;
1231 ret = PTR_ERR(host->rx_chan);
1234 host->rx_chan = NULL;
1240 static struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1243 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
1246 static int sdhci_external_dma_setup(struct sdhci_host *host,
1258 if (!host->mapbase)
1262 cfg.src_addr = host->mapbase + SDHCI_BUFFER;
1263 cfg.dst_addr = host->mapbase + SDHCI_BUFFER;
1275 chan = sdhci_external_dma_channel(host, data);
1281 sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1301 static void sdhci_external_dma_release(struct sdhci_host *host)
1303 if (host->tx_chan) {
1304 dma_release_channel(host->tx_chan);
1305 host->tx_chan = NULL;
1308 if (host->rx_chan) {
1309 dma_release_channel(host->rx_chan);
1310 host->rx_chan = NULL;
1313 sdhci_switch_external_dma(host, false);
1316 static void __sdhci_external_dma_prepare_data(struct sdhci_host *host,
1321 sdhci_initialize_data(host, data);
1323 host->flags |= SDHCI_REQ_USE_DMA;
1324 sdhci_set_transfer_irqs(host);
1326 sdhci_set_block_info(host, data);
1329 static void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1332 if (!sdhci_external_dma_setup(host, cmd)) {
1333 __sdhci_external_dma_prepare_data(host, cmd);
1335 sdhci_external_dma_release(host);
1337 mmc_hostname(host->mmc));
1338 sdhci_prepare_data(host, cmd);
1342 static void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1350 chan = sdhci_external_dma_channel(host, cmd->data);
1357 static inline int sdhci_external_dma_init(struct sdhci_host *host)
1362 static inline void sdhci_external_dma_release(struct sdhci_host *host)
1366 static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
1373 static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
1378 static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
1386 void sdhci_switch_external_dma(struct sdhci_host *host, bool en)
1388 host->use_external_dma = en;
1392 static inline bool sdhci_auto_cmd12(struct sdhci_host *host,
1395 return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
1399 static inline bool sdhci_auto_cmd23(struct sdhci_host *host,
1402 return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
1405 static inline bool sdhci_manual_cmd23(struct sdhci_host *host,
1408 return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
1411 static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
1415 bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) &&
1417 bool use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
1426 if (host->version >= SDHCI_SPEC_410 && host->v4_mode &&
1430 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1435 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
1450 static void sdhci_set_transfer_mode(struct sdhci_host *host,
1457 if (host->quirks2 &
1461 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1464 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
1465 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
1471 WARN_ON(!host->data);
1473 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
1478 sdhci_auto_cmd_select(host, cmd, &mode);
1479 if (sdhci_auto_cmd23(host, cmd->mrq))
1480 sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
1485 if (host->flags & SDHCI_REQ_USE_DMA)
1488 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
1491 static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq)
1493 return (!(host->flags & SDHCI_DEVICE_DEAD) &&
1497 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
1500 static void sdhci_set_mrq_done(struct sdhci_host *host, struct mmc_request *mrq)
1505 if (host->mrqs_done[i] == mrq) {
1512 if (!host->mrqs_done[i]) {
1513 host->mrqs_done[i] = mrq;
1521 static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1523 if (host->cmd && host->cmd->mrq == mrq)
1524 host->cmd = NULL;
1526 if (host->data_cmd && host->data_cmd->mrq == mrq)
1527 host->data_cmd = NULL;
1529 if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
1530 host->deferred_cmd = NULL;
1532 if (host->data && host->data->mrq == mrq)
1533 host->data = NULL;
1535 if (sdhci_needs_reset(host, mrq))
1536 host->pending_reset = true;
1538 sdhci_set_mrq_done(host, mrq);
1540 sdhci_del_timer(host, mrq);
1542 if (!sdhci_has_requests(host))
1543 sdhci_led_deactivate(host);
1546 static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq)
1548 __sdhci_finish_mrq(host, mrq);
1550 queue_work(host->complete_wq, &host->complete_work);
1553 static void __sdhci_finish_data(struct sdhci_host *host, bool sw_data_timeout)
1555 struct mmc_command *data_cmd = host->data_cmd;
1556 struct mmc_data *data = host->data;
1558 host->data = NULL;
1559 host->data_cmd = NULL;
1566 if (!host->cmd || host->cmd == data_cmd)
1567 sdhci_reset_for(host, REQUEST_ERROR);
1569 sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
1572 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
1574 sdhci_adma_table_post(host, data);
1594 ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) ||
1602 __sdhci_finish_mrq(host, data->mrq);
1605 host->cmd = NULL;
1606 if (!sdhci_send_command(host, data->stop)) {
1613 __sdhci_finish_mrq(host, data->mrq);
1615 WARN_ON(host->deferred_cmd);
1616 host->deferred_cmd = data->stop;
1621 __sdhci_finish_mrq(host, data->mrq);
1625 static void sdhci_finish_data(struct sdhci_host *host)
1627 __sdhci_finish_data(host, false);
1630 static bool sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1636 WARN_ON(host->cmd);
1641 if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
1654 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
1657 host->cmd = cmd;
1658 host->data_timeout = 0;
1660 WARN_ON(host->data_cmd);
1661 host->data_cmd = cmd;
1662 sdhci_set_timeout(host, cmd);
1666 if (host->use_external_dma)
1667 sdhci_external_dma_prepare_data(host, cmd);
1669 sdhci_prepare_data(host, cmd);
1672 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1674 sdhci_set_transfer_mode(host, cmd);
1705 if (host->data_timeout)
1706 timeout += nsecs_to_jiffies(host->data_timeout);
1711 sdhci_mod_timer(host, cmd->mrq, timeout);
1713 if (host->use_external_dma)
1714 sdhci_external_dma_pre_transfer(host, cmd);
1716 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1721 static bool sdhci_present_error(struct sdhci_host *host,
1724 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1732 static bool sdhci_send_command_retry(struct sdhci_host *host,
1735 __releases(host->lock)
1736 __acquires(host->lock)
1738 struct mmc_command *deferred_cmd = host->deferred_cmd;
1742 while (!sdhci_send_command(host, cmd)) {
1745 mmc_hostname(host->mmc));
1746 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1747 sdhci_dumpregs(host);
1752 spin_unlock_irqrestore(&host->lock, flags);
1756 present = host->mmc->ops->get_cd(host->mmc);
1758 spin_lock_irqsave(&host->lock, flags);
1761 if (cmd == deferred_cmd && cmd != host->deferred_cmd)
1764 if (sdhci_present_error(host, cmd, present))
1768 if (cmd == host->deferred_cmd)
1769 host->deferred_cmd = NULL;
1774 static void sdhci_read_rsp_136(struct sdhci_host *host, struct mmc_command *cmd)
1780 cmd->resp[i] = sdhci_readl(host, reg);
1783 if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
1794 static void sdhci_finish_command(struct sdhci_host *host)
1796 struct mmc_command *cmd = host->cmd;
1798 host->cmd = NULL;
1802 sdhci_read_rsp_136(host, cmd);
1804 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1809 mmc_command_done(host->mmc, cmd->mrq);
1812 * The host can send and interrupt when the busy state has
1824 } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) &&
1825 cmd == host->data_cmd) {
1833 if (!sdhci_send_command(host, cmd->mrq->cmd)) {
1834 WARN_ON(host->deferred_cmd);
1835 host->deferred_cmd = cmd->mrq->cmd;
1840 if (host->data && host->data_early)
1841 sdhci_finish_data(host);
1844 __sdhci_finish_mrq(host, cmd->mrq);
1848 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1852 switch (host->timing) {
1855 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
1858 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1861 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1864 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1868 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1872 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1875 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1879 mmc_hostname(host->mmc));
1880 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1886 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1894 if (host->version >= SDHCI_SPEC_300) {
1895 if (host->preset_enabled) {
1898 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1899 pre_val = sdhci_get_preset_value(host);
1901 if (host->clk_mul &&
1905 clk_mul = host->clk_mul;
1916 if (host->clk_mul) {
1918 if ((host->max_clk * host->clk_mul / div)
1922 if ((host->max_clk * host->clk_mul / div) <= clock) {
1929 clk_mul = host->clk_mul;
1940 if (!host->clk_mul || switch_base_clk) {
1942 if (host->max_clk <= clock)
1947 if ((host->max_clk / div) <= clock)
1953 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1954 && !div && host->max_clk <= 25000000)
1960 if ((host->max_clk / div) <= clock)
1969 *actual_clock = (host->max_clk * clk_mul) / real_div;
1978 void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
1983 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1990 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1995 mmc_hostname(host->mmc));
1996 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
1997 sdhci_dumpregs(host);
2003 if (host->version >= SDHCI_SPEC_410 && host->v4_mode) {
2006 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2013 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2018 mmc_hostname(host->mmc));
2019 sdhci_err_stats_inc(host, CTRL_TIMEOUT);
2020 sdhci_dumpregs(host);
2028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2032 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
2036 host->mmc->actual_clock = 0;
2038 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
2043 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
2044 sdhci_enable_clk(host, clk);
2048 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
2051 struct mmc_host *mmc = host->mmc;
2056 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
2058 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2061 void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
2094 mmc_hostname(host->mmc), vdd);
2099 if (host->pwr == pwr)
2102 host->pwr = pwr;
2105 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2106 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2107 sdhci_runtime_pm_bus_off(host);
2113 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
2114 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
2121 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
2122 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2126 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
2128 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
2129 sdhci_runtime_pm_bus_on(host);
2135 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
2141 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
2144 if (IS_ERR(host->mmc->supply.vmmc))
2145 sdhci_set_power_noreg(host, mode, vdd);
2147 sdhci_set_power_reg(host, mode, vdd);
2157 void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
2161 if (!IS_ERR(host->mmc->supply.vmmc)) {
2162 struct mmc_host *mmc = host->mmc;
2166 sdhci_set_power_noreg(host, mode, vdd);
2178 struct sdhci_host *host = mmc_priv(mmc);
2186 spin_lock_irqsave(&host->lock, flags);
2188 sdhci_led_activate(host);
2190 if (sdhci_present_error(host, mrq->cmd, present))
2193 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2195 if (!sdhci_send_command_retry(host, cmd, flags))
2198 spin_unlock_irqrestore(&host->lock, flags);
2203 sdhci_finish_mrq(host, mrq);
2204 spin_unlock_irqrestore(&host->lock, flags);
2210 struct sdhci_host *host = mmc_priv(mmc);
2215 spin_lock_irqsave(&host->lock, flags);
2217 if (sdhci_present_error(host, mrq->cmd, true)) {
2218 sdhci_finish_mrq(host, mrq);
2222 cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
2231 if (!sdhci_send_command(host, cmd))
2234 sdhci_led_activate(host);
2237 spin_unlock_irqrestore(&host->lock, flags);
2242 void sdhci_set_bus_width(struct sdhci_host *host, int width)
2246 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2251 if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
2258 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2262 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
2266 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2267 /* Select Bus Speed Mode for host */
2283 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2301 static bool sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
2303 return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
2307 static bool sdhci_presetable_values_change(struct sdhci_host *host, struct mmc_ios *ios)
2314 return !host->preset_enabled &&
2315 (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
2320 struct sdhci_host *host = mmc_priv(mmc);
2321 bool reinit_uhs = host->reinit_uhs;
2325 host->reinit_uhs = false;
2330 if (host->flags & SDHCI_DEVICE_DEAD) {
2342 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2343 sdhci_reinit(host);
2346 if (host->version >= SDHCI_SPEC_300 &&
2348 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
2349 sdhci_enable_preset_value(host, false);
2351 if (!ios->clock || ios->clock != host->clock) {
2352 turning_on_clk = ios->clock && !host->clock;
2354 host->ops->set_clock(host, ios->clock);
2355 host->clock = ios->clock;
2357 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
2358 host->clock) {
2359 host->timeout_clk = mmc->actual_clock ?
2361 host->clock / 1000;
2363 host->ops->get_max_timeout_count ?
2364 host->ops->get_max_timeout_count(host) :
2366 mmc->max_busy_timeout /= host->timeout_clk;
2370 if (host->ops->set_power)
2371 host->ops->set_power(host, ios->power_mode, ios->vdd);
2373 sdhci_set_power(host, ios->power_mode, ios->vdd);
2375 if (host->ops->platform_send_init_74_clocks)
2376 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
2378 host->ops->set_bus_width(host, ios->bus_width);
2386 host->timing == ios->timing &&
2387 host->version >= SDHCI_SPEC_300 &&
2388 !sdhci_presetable_values_change(host, ios))
2391 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
2393 if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) {
2408 if (host->version >= SDHCI_SPEC_300) {
2417 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
2420 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
2423 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2425 if (!host->preset_enabled) {
2430 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2446 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
2447 host->drv_type = ios->drv_type;
2450 host->ops->set_uhs_signaling(host, ios->timing);
2451 host->timing = ios->timing;
2453 if (sdhci_preset_needed(host, ios->timing)) {
2456 sdhci_enable_preset_value(host, true);
2457 preset = sdhci_get_preset_value(host);
2460 host->drv_type = ios->drv_type;
2464 host->ops->set_clock(host, host->clock);
2466 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
2472 struct sdhci_host *host = mmc_priv(mmc);
2475 if (host->flags & SDHCI_DEVICE_DEAD)
2490 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2494 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2499 struct sdhci_host *host = mmc_priv(mmc);
2503 spin_lock_irqsave(&host->lock, flags);
2505 if (host->flags & SDHCI_DEVICE_DEAD)
2508 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
2510 spin_unlock_irqrestore(&host->lock, flags);
2516 static int sdhci_check_ro(struct sdhci_host *host)
2521 spin_lock_irqsave(&host->lock, flags);
2523 if (host->flags & SDHCI_DEVICE_DEAD)
2525 else if (host->ops->get_ro)
2526 is_readonly = host->ops->get_ro(host);
2527 else if (mmc_can_gpio_ro(host->mmc))
2528 is_readonly = mmc_gpio_get_ro(host->mmc);
2530 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
2533 spin_unlock_irqrestore(&host->lock, flags);
2536 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
2544 struct sdhci_host *host = mmc_priv(mmc);
2547 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
2548 return sdhci_check_ro(host);
2552 if (sdhci_check_ro(host)) {
2563 struct sdhci_host *host = mmc_priv(mmc);
2565 if (host->ops && host->ops->hw_reset)
2566 host->ops->hw_reset(host);
2569 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
2571 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
2573 host->ier |= SDHCI_INT_CARD_INT;
2575 host->ier &= ~SDHCI_INT_CARD_INT;
2577 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2578 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2584 struct sdhci_host *host = mmc_priv(mmc);
2590 spin_lock_irqsave(&host->lock, flags);
2591 sdhci_enable_sdio_irq_nolock(host, enable);
2592 spin_unlock_irqrestore(&host->lock, flags);
2601 struct sdhci_host *host = mmc_priv(mmc);
2604 spin_lock_irqsave(&host->lock, flags);
2605 sdhci_enable_sdio_irq_nolock(host, true);
2606 spin_unlock_irqrestore(&host->lock, flags);
2612 struct sdhci_host *host = mmc_priv(mmc);
2620 if (host->version < SDHCI_SPEC_300)
2623 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2627 if (!(host->flags & SDHCI_SIGNALING_330))
2631 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2645 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2654 if (!(host->flags & SDHCI_SIGNALING_180))
2670 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2673 if (host->ops->voltage_switch)
2674 host->ops->voltage_switch(host);
2677 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2686 if (!(host->flags & SDHCI_SIGNALING_120))
2706 struct sdhci_host *host = mmc_priv(mmc);
2710 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
2717 struct sdhci_host *host = mmc_priv(mmc);
2720 spin_lock_irqsave(&host->lock, flags);
2721 host->flags |= SDHCI_HS400_TUNING;
2722 spin_unlock_irqrestore(&host->lock, flags);
2727 void sdhci_start_tuning(struct sdhci_host *host)
2731 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2733 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
2735 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2747 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
2748 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
2752 void sdhci_end_tuning(struct sdhci_host *host)
2754 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2755 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2759 void sdhci_reset_tuning(struct sdhci_host *host)
2763 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2766 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2770 void sdhci_abort_tuning(struct sdhci_host *host, u32 opcode)
2772 sdhci_reset_tuning(host);
2774 sdhci_reset_for(host, TUNING_ABORT);
2776 sdhci_end_tuning(host);
2778 mmc_send_abort_tuning(host->mmc, opcode);
2789 void sdhci_send_tuning(struct sdhci_host *host, u32 opcode)
2791 struct mmc_host *mmc = host->mmc;
2795 u32 b = host->sdma_boundary;
2797 spin_lock_irqsave(&host->lock, flags);
2811 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
2813 sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
2816 * The tuning block is sent by the card to the host controller.
2821 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2823 if (!sdhci_send_command_retry(host, &cmd, flags)) {
2824 spin_unlock_irqrestore(&host->lock, flags);
2825 host->tuning_done = 0;
2829 host->cmd = NULL;
2831 sdhci_del_timer(host, &mrq);
2833 host->tuning_done = 0;
2835 spin_unlock_irqrestore(&host->lock, flags);
2838 wait_event_timeout(host->buf_ready_int, (host->tuning_done == 1),
2844 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
2852 for (i = 0; i < host->tuning_loop_count; i++) {
2855 sdhci_send_tuning(host, opcode);
2857 if (!host->tuning_done) {
2859 mmc_hostname(host->mmc));
2860 sdhci_abort_tuning(host, opcode);
2865 if (host->tuning_delay > 0)
2866 mdelay(host->tuning_delay);
2868 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2878 mmc_hostname(host->mmc));
2879 sdhci_reset_tuning(host);
2886 struct sdhci_host *host = mmc_priv(mmc);
2891 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
2893 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2894 tuning_count = host->tuning_count;
2903 switch (host->timing) {
2923 if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
2931 if (host->ops->platform_execute_tuning) {
2932 err = host->ops->platform_execute_tuning(host, opcode);
2938 if (host->tuning_delay < 0)
2939 host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
2941 sdhci_start_tuning(host);
2943 host->tuning_err = __sdhci_execute_tuning(host, opcode);
2945 sdhci_end_tuning(host);
2947 host->flags &= ~SDHCI_HS400_TUNING;
2953 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2956 if (host->version < SDHCI_SPEC_300)
2963 if (host->preset_enabled != enable) {
2964 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2974 host->flags |= SDHCI_PV_ENABLED;
2976 host->flags &= ~SDHCI_PV_ENABLED;
2978 host->preset_enabled = enable;
2996 struct sdhci_host *host = mmc_priv(mmc);
3005 if (host->flags & SDHCI_REQ_USE_DMA && !host->bounce_buffer)
3006 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
3009 static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
3011 if (host->data_cmd) {
3012 host->data_cmd->error = err;
3013 sdhci_finish_mrq(host, host->data_cmd->mrq);
3016 if (host->cmd) {
3017 host->cmd->error = err;
3018 sdhci_finish_mrq(host, host->cmd->mrq);
3024 struct sdhci_host *host = mmc_priv(mmc);
3029 if (host->ops->card_event)
3030 host->ops->card_event(host);
3034 spin_lock_irqsave(&host->lock, flags);
3037 if (sdhci_has_requests(host) && !present) {
3043 sdhci_reset_for(host, CARD_REMOVED);
3045 sdhci_error_out_mrqs(host, -ENOMEDIUM);
3048 spin_unlock_irqrestore(&host->lock, flags);
3074 static bool sdhci_request_done(struct sdhci_host *host)
3080 spin_lock_irqsave(&host->lock, flags);
3083 mrq = host->mrqs_done[i];
3089 spin_unlock_irqrestore(&host->lock, flags);
3097 if (sdhci_needs_reset(host, mrq)) {
3101 * also be in mrqs_done, otherwise host->cmd and host->data_cmd
3104 if (host->cmd || host->data_cmd) {
3105 spin_unlock_irqrestore(&host->lock, flags);
3110 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
3112 host->ops->set_clock(host, host->clock);
3114 sdhci_reset_for(host, REQUEST_ERROR);
3116 host->pending_reset = false;
3124 if (host->flags & SDHCI_REQ_USE_DMA) {
3127 if (host->use_external_dma && data &&
3129 struct dma_chan *chan = sdhci_external_dma_channel(host, data);
3131 host->mrqs_done[i] = NULL;
3132 spin_unlock_irqrestore(&host->lock, flags);
3134 spin_lock_irqsave(&host->lock, flags);
3135 sdhci_set_mrq_done(host, mrq);
3139 if (host->bounce_buffer) {
3147 if (length > host->bounce_buffer_size) {
3149 mmc_hostname(host->mmc),
3150 host->bounce_buffer_size,
3153 length = host->bounce_buffer_size;
3156 mmc_dev(host->mmc),
3157 host->bounce_addr,
3158 host->bounce_buffer_size,
3162 host->bounce_buffer,
3167 mmc_dev(host->mmc),
3168 host->bounce_addr,
3169 host->bounce_buffer_size,
3174 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
3182 host->mrqs_done[i] = NULL;
3184 spin_unlock_irqrestore(&host->lock, flags);
3186 if (host->ops->request_done)
3187 host->ops->request_done(host, mrq);
3189 mmc_request_done(host->mmc, mrq);
3196 struct sdhci_host *host = container_of(work, struct sdhci_host,
3199 while (!sdhci_request_done(host))
3205 struct sdhci_host *host;
3208 host = from_timer(host, t, timer);
3210 spin_lock_irqsave(&host->lock, flags);
3212 if (host->cmd && !sdhci_data_line_cmd(host->cmd)) {
3214 mmc_hostname(host->mmc));
3215 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3216 sdhci_dumpregs(host);
3218 host->cmd->error = -ETIMEDOUT;
3219 sdhci_finish_mrq(host, host->cmd->mrq);
3222 spin_unlock_irqrestore(&host->lock, flags);
3227 struct sdhci_host *host;
3230 host = from_timer(host, t, data_timer);
3232 spin_lock_irqsave(&host->lock, flags);
3234 if (host->data || host->data_cmd ||
3235 (host->cmd && sdhci_data_line_cmd(host->cmd))) {
3237 mmc_hostname(host->mmc));
3238 sdhci_err_stats_inc(host, REQ_TIMEOUT);
3239 sdhci_dumpregs(host);
3241 if (host->data) {
3242 host->data->error = -ETIMEDOUT;
3243 __sdhci_finish_data(host, true);
3244 queue_work(host->complete_wq, &host->complete_work);
3245 } else if (host->data_cmd) {
3246 host->data_cmd->error = -ETIMEDOUT;
3247 sdhci_finish_mrq(host, host->data_cmd->mrq);
3249 host->cmd->error = -ETIMEDOUT;
3250 sdhci_finish_mrq(host, host->cmd->mrq);
3254 spin_unlock_irqrestore(&host->lock, flags);
3263 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p)
3266 if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd) {
3267 struct mmc_request *mrq = host->data_cmd->mrq;
3268 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3274 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
3280 if (!host->cmd) {
3286 if (host->pending_reset)
3289 mmc_hostname(host->mmc), (unsigned)intmask);
3290 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3291 sdhci_dumpregs(host);
3298 host->cmd->error = -ETIMEDOUT;
3299 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3301 host->cmd->error = -EILSEQ;
3302 if (!mmc_op_tuning(host->cmd->opcode))
3303 sdhci_err_stats_inc(host, CMD_CRC);
3306 if (host->cmd->data &&
3309 host->cmd = NULL;
3314 __sdhci_finish_mrq(host, host->cmd->mrq);
3320 struct mmc_request *mrq = host->cmd->mrq;
3321 u16 auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
3326 sdhci_err_stats_inc(host, AUTO_CMD);
3328 if (sdhci_auto_cmd23(host, mrq)) {
3330 __sdhci_finish_mrq(host, mrq);
3336 sdhci_finish_command(host);
3339 static void sdhci_adma_show_error(struct sdhci_host *host)
3341 void *desc = host->adma_table;
3342 dma_addr_t dma = host->adma_addr;
3344 sdhci_dumpregs(host);
3349 if (host->flags & SDHCI_USE_64_BIT_DMA)
3363 desc += host->desc_sz;
3364 dma += host->desc_sz;
3371 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
3380 if (intmask & SDHCI_INT_DATA_AVAIL && !host->data) {
3381 if (mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)))) {
3382 host->tuning_done = 1;
3383 wake_up(&host->buf_ready_int);
3388 if (!host->data) {
3389 struct mmc_command *data_cmd = host->data_cmd;
3398 host->data_cmd = NULL;
3400 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3401 __sdhci_finish_mrq(host, data_cmd->mrq);
3405 host->data_cmd = NULL;
3411 if (host->cmd == data_cmd)
3414 __sdhci_finish_mrq(host, data_cmd->mrq);
3424 if (host->pending_reset)
3428 mmc_hostname(host->mmc), (unsigned)intmask);
3429 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3430 sdhci_dumpregs(host);
3436 host->data->error = -ETIMEDOUT;
3437 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3439 host->data->error = -EILSEQ;
3440 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3441 sdhci_err_stats_inc(host, DAT_CRC);
3443 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
3445 host->data->error = -EILSEQ;
3446 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3447 sdhci_err_stats_inc(host, DAT_CRC);
3449 pr_err("%s: ADMA error: 0x%08x\n", mmc_hostname(host->mmc),
3451 sdhci_adma_show_error(host);
3452 sdhci_err_stats_inc(host, ADMA);
3453 host->data->error = -EIO;
3454 if (host->ops->adma_workaround)
3455 host->ops->adma_workaround(host, intmask);
3458 if (host->data->error)
3459 sdhci_finish_data(host);
3462 sdhci_transfer_pio(host);
3469 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
3476 dmastart = sdhci_sdma_address(host);
3477 dmanow = dmastart + host->data->bytes_xfered;
3484 host->data->bytes_xfered = dmanow - dmastart;
3486 &dmastart, host->data->bytes_xfered, &dmanow);
3487 sdhci_set_sdma_addr(host, dmanow);
3491 if (host->cmd == host->data_cmd) {
3497 host->data_early = 1;
3499 sdhci_finish_data(host);
3505 static inline bool sdhci_defer_done(struct sdhci_host *host,
3510 return host->pending_reset || host->always_defer_done ||
3511 ((host->flags & SDHCI_REQ_USE_DMA) && data &&
3519 struct sdhci_host *host = dev_id;
3524 spin_lock(&host->lock);
3526 if (host->runtime_suspended) {
3527 spin_unlock(&host->lock);
3531 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3540 if (host->ops->irq) {
3541 intmask = host->ops->irq(host, intmask);
3549 sdhci_writel(host, mask, SDHCI_INT_STATUS);
3552 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
3566 host->ier &= ~(SDHCI_INT_CARD_INSERT |
3568 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
3570 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3571 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3573 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
3576 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
3582 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
3585 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
3589 mmc_hostname(host->mmc));
3592 mmc_retune_needed(host->mmc);
3595 (host->ier & SDHCI_INT_CARD_INT)) {
3596 sdhci_enable_sdio_irq_nolock(host, false);
3597 sdio_signal_irq(host->mmc);
3607 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
3613 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
3618 struct mmc_request *mrq = host->mrqs_done[i];
3623 if (sdhci_defer_done(host, mrq)) {
3627 host->mrqs_done[i] = NULL;
3631 if (host->deferred_cmd)
3634 spin_unlock(&host->lock);
3641 if (host->ops->request_done)
3642 host->ops->request_done(host, mrqs_done[i]);
3644 mmc_request_done(host->mmc, mrqs_done[i]);
3649 mmc_hostname(host->mmc), unexpected);
3650 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
3651 sdhci_dumpregs(host);
3659 struct sdhci_host *host = dev_id;
3664 while (!sdhci_request_done(host))
3667 spin_lock_irqsave(&host->lock, flags);
3669 isr = host->thread_isr;
3670 host->thread_isr = 0;
3672 cmd = host->deferred_cmd;
3673 if (cmd && !sdhci_send_command_retry(host, cmd, flags))
3674 sdhci_finish_mrq(host, cmd->mrq);
3676 spin_unlock_irqrestore(&host->lock, flags);
3679 struct mmc_host *mmc = host->mmc;
3696 static bool sdhci_cd_irq_can_wakeup(struct sdhci_host *host)
3698 return mmc_card_is_removable(host->mmc) &&
3699 !(host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3700 !mmc_can_gpio_cd(host->mmc);
3711 static bool sdhci_enable_irq_wakeups(struct sdhci_host *host)
3719 if (sdhci_cd_irq_can_wakeup(host)) {
3724 if (mmc_card_wake_sdio_irq(host->mmc)) {
3732 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3735 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3737 sdhci_writel(host, irq_val, SDHCI_INT_ENABLE);
3739 host->irq_wake_enabled = !enable_irq_wake(host->irq);
3741 return host->irq_wake_enabled;
3744 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
3750 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
3752 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
3754 disable_irq_wake(host->irq);
3756 host->irq_wake_enabled = false;
3759 int sdhci_suspend_host(struct sdhci_host *host)
3761 sdhci_disable_card_detection(host);
3763 mmc_retune_timer_stop(host->mmc);
3765 if (!device_may_wakeup(mmc_dev(host->mmc)) ||
3766 !sdhci_enable_irq_wakeups(host)) {
3767 host->ier = 0;
3768 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3769 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3770 free_irq(host->irq, host);
3778 int sdhci_resume_host(struct sdhci_host *host)
3780 struct mmc_host *mmc = host->mmc;
3783 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
3784 if (host->ops->enable_dma)
3785 host->ops->enable_dma(host);
3789 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
3790 /* Card keeps power but host controller does not */
3791 sdhci_init(host, 0);
3792 host->pwr = 0;
3793 host->clock = 0;
3794 host->reinit_uhs = true;
3797 sdhci_init(host, (mmc->pm_flags & MMC_PM_KEEP_POWER));
3800 if (host->irq_wake_enabled) {
3801 sdhci_disable_irq_wakeups(host);
3803 ret = request_threaded_irq(host->irq, sdhci_irq,
3805 mmc_hostname(mmc), host);
3810 sdhci_enable_card_detection(host);
3817 int sdhci_runtime_suspend_host(struct sdhci_host *host)
3821 mmc_retune_timer_stop(host->mmc);
3823 spin_lock_irqsave(&host->lock, flags);
3824 host->ier &= SDHCI_INT_CARD_INT;
3825 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3826 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3827 spin_unlock_irqrestore(&host->lock, flags);
3829 synchronize_hardirq(host->irq);
3831 spin_lock_irqsave(&host->lock, flags);
3832 host->runtime_suspended = true;
3833 spin_unlock_irqrestore(&host->lock, flags);
3839 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset)
3841 struct mmc_host *mmc = host->mmc;
3843 int host_flags = host->flags;
3846 if (host->ops->enable_dma)
3847 host->ops->enable_dma(host);
3850 sdhci_init(host, soft_reset);
3855 host->pwr = 0;
3856 host->clock = 0;
3857 host->reinit_uhs = true;
3862 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
3863 spin_lock_irqsave(&host->lock, flags);
3864 sdhci_enable_preset_value(host, true);
3865 spin_unlock_irqrestore(&host->lock, flags);
3873 spin_lock_irqsave(&host->lock, flags);
3875 host->runtime_suspended = false;
3879 sdhci_enable_sdio_irq_nolock(host, true);
3882 sdhci_enable_card_detection(host);
3884 spin_unlock_irqrestore(&host->lock, flags);
3900 struct sdhci_host *host = mmc_priv(mmc);
3904 spin_lock_irqsave(&host->lock, flags);
3906 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
3913 if (host->v4_mode && (host->caps1 & SDHCI_CAN_DO_ADMA3))
3915 else if (host->flags & SDHCI_USE_64_BIT_DMA)
3919 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
3921 sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512),
3925 sdhci_set_timeout(host, NULL);
3927 host->ier = host->cqe_ier;
3929 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
3930 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
3932 host->cqe_on = true;
3935 mmc_hostname(mmc), host->ier,
3936 sdhci_readl(host, SDHCI_INT_STATUS));
3938 spin_unlock_irqrestore(&host->lock, flags);
3944 struct sdhci_host *host = mmc_priv(mmc);
3947 spin_lock_irqsave(&host->lock, flags);
3949 sdhci_set_default_irqs(host);
3951 host->cqe_on = false;
3954 sdhci_reset_for(host, CQE_RECOVERY);
3957 mmc_hostname(mmc), host->ier,
3958 sdhci_readl(host, SDHCI_INT_STATUS));
3960 spin_unlock_irqrestore(&host->lock, flags);
3964 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
3969 if (!host->cqe_on)
3974 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3975 sdhci_err_stats_inc(host, CMD_CRC);
3978 sdhci_err_stats_inc(host, CMD_TIMEOUT);
3984 if (!mmc_op_tuning(SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))))
3985 sdhci_err_stats_inc(host, DAT_CRC);
3988 sdhci_err_stats_inc(host, DAT_TIMEOUT);
3991 sdhci_err_stats_inc(host, ADMA);
3996 mask = intmask & host->cqe_ier;
3997 sdhci_writel(host, mask, SDHCI_INT_STATUS);
4001 mmc_hostname(host->mmc));
4003 intmask &= ~(host->cqe_ier | SDHCI_INT_ERROR);
4005 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
4007 mmc_hostname(host->mmc), intmask);
4008 sdhci_err_stats_inc(host, UNEXPECTED_IRQ);
4009 sdhci_dumpregs(host);
4026 struct sdhci_host *host;
4034 host = mmc_priv(mmc);
4035 host->mmc = mmc;
4036 host->mmc_host_ops = sdhci_ops;
4037 mmc->ops = &host->mmc_host_ops;
4039 host->flags = SDHCI_SIGNALING_330;
4041 host->cqe_ier = SDHCI_CQE_INT_MASK;
4042 host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
4044 host->tuning_delay = -1;
4045 host->tuning_loop_count = MAX_TUNING_LOOP;
4047 host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
4054 host->adma_table_cnt = SDHCI_MAX_SEGS * 2 + 1;
4055 host->max_adma = 65536;
4057 host->max_timeout_count = 0xE;
4059 return host;
4064 static int sdhci_set_dma_mask(struct sdhci_host *host)
4066 struct mmc_host *mmc = host->mmc;
4070 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
4071 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4074 if (host->flags & SDHCI_USE_64_BIT_DMA) {
4079 host->flags &= ~SDHCI_USE_64_BIT_DMA;
4094 void __sdhci_read_caps(struct sdhci_host *host, const u16 *ver,
4101 if (host->read_caps)
4104 host->read_caps = true;
4107 host->quirks = debug_quirks;
4110 host->quirks2 = debug_quirks2;
4112 sdhci_reset_for_all(host);
4114 if (host->v4_mode)
4115 sdhci_do_enable_v4_mode(host);
4117 device_property_read_u64(mmc_dev(host->mmc),
4119 device_property_read_u64(mmc_dev(host->mmc),
4122 v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
4123 host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
4126 host->caps = *caps;
4128 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
4129 host->caps &= ~lower_32_bits(dt_caps_mask);
4130 host->caps |= lower_32_bits(dt_caps);
4133 if (host->version < SDHCI_SPEC_300)
4137 host->caps1 = *caps1;
4139 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
4140 host->caps1 &= ~upper_32_bits(dt_caps_mask);
4141 host->caps1 |= upper_32_bits(dt_caps);
4146 static void sdhci_allocate_bounce_buffer(struct sdhci_host *host)
4148 struct mmc_host *mmc = host->mmc;
4173 host->bounce_buffer = devm_kmalloc(mmc_dev(mmc),
4176 if (!host->bounce_buffer) {
4187 host->bounce_addr = dma_map_single(mmc_dev(mmc),
4188 host->bounce_buffer,
4191 ret = dma_mapping_error(mmc_dev(mmc), host->bounce_addr);
4193 devm_kfree(mmc_dev(mmc), host->bounce_buffer);
4194 host->bounce_buffer = NULL;
4199 host->bounce_buffer_size = bounce_size;
4210 static inline bool sdhci_can_64bit_dma(struct sdhci_host *host)
4217 if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
4218 return host->caps & SDHCI_CAN_64BIT_V4;
4220 return host->caps & SDHCI_CAN_64BIT;
4223 int sdhci_setup_host(struct sdhci_host *host)
4233 WARN_ON(host == NULL);
4234 if (host == NULL)
4237 mmc = host->mmc;
4241 * early before resetting the host and reading the capabilities so that
4242 * the host can take the appropriate action if regulators are not
4253 sdhci_readw(host, SDHCI_HOST_VERSION),
4254 sdhci_readl(host, SDHCI_PRESENT_STATE));
4256 sdhci_readl(host, SDHCI_CAPABILITIES),
4257 sdhci_readl(host, SDHCI_CAPABILITIES_1));
4259 sdhci_read_caps(host);
4261 override_timeout_clk = host->timeout_clk;
4263 if (host->version > SDHCI_SPEC_420) {
4265 mmc_hostname(mmc), host->version);
4268 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
4269 host->flags |= SDHCI_USE_SDMA;
4270 else if (!(host->caps & SDHCI_CAN_DO_SDMA))
4273 host->flags |= SDHCI_USE_SDMA;
4275 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
4276 (host->flags & SDHCI_USE_SDMA)) {
4278 host->flags &= ~SDHCI_USE_SDMA;
4281 if ((host->version >= SDHCI_SPEC_200) &&
4282 (host->caps & SDHCI_CAN_DO_ADMA2))
4283 host->flags |= SDHCI_USE_ADMA;
4285 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
4286 (host->flags & SDHCI_USE_ADMA)) {
4288 host->flags &= ~SDHCI_USE_ADMA;
4291 if (sdhci_can_64bit_dma(host))
4292 host->flags |= SDHCI_USE_64_BIT_DMA;
4294 if (host->use_external_dma) {
4295 ret = sdhci_external_dma_init(host);
4303 sdhci_switch_external_dma(host, false);
4306 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4309 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
4310 if (host->ops->set_dma_mask)
4311 ret = host->ops->set_dma_mask(host);
4313 ret = sdhci_set_dma_mask(host);
4315 if (!ret && host->ops->enable_dma)
4316 ret = host->ops->enable_dma(host);
4321 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
4328 if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
4329 host->flags &= ~SDHCI_USE_SDMA;
4331 if (host->flags & SDHCI_USE_ADMA) {
4335 if (!(host->flags & SDHCI_USE_64_BIT_DMA))
4336 host->alloc_desc_sz = SDHCI_ADMA2_32_DESC_SZ;
4337 else if (!host->alloc_desc_sz)
4338 host->alloc_desc_sz = SDHCI_ADMA2_64_DESC_SZ(host);
4340 host->desc_sz = host->alloc_desc_sz;
4341 host->adma_table_sz = host->adma_table_cnt * host->desc_sz;
4343 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
4349 host->align_buffer_sz + host->adma_table_sz,
4354 host->flags &= ~SDHCI_USE_ADMA;
4355 } else if ((dma + host->align_buffer_sz) &
4359 host->flags &= ~SDHCI_USE_ADMA;
4360 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4361 host->adma_table_sz, buf, dma);
4363 host->align_buffer = buf;
4364 host->align_addr = dma;
4366 host->adma_table = buf + host->align_buffer_sz;
4367 host->adma_addr = dma + host->align_buffer_sz;
4376 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
4377 host->dma_mask = DMA_BIT_MASK(64);
4378 mmc_dev(mmc)->dma_mask = &host->dma_mask;
4381 if (host->version >= SDHCI_SPEC_300)
4382 host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
4384 host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
4386 host->max_clk *= 1000000;
4387 if (host->max_clk == 0 || host->quirks &
4389 if (!host->ops->get_max_clock) {
4395 host->max_clk = host->ops->get_max_clock(host);
4402 host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
4410 if (host->clk_mul)
4411 host->clk_mul += 1;
4414 * Set host parameters.
4416 max_clk = host->max_clk;
4418 if (host->ops->get_min_clock)
4419 mmc->f_min = host->ops->get_min_clock(host);
4420 else if (host->version >= SDHCI_SPEC_300) {
4421 if (host->clk_mul)
4422 max_clk = host->max_clk * host->clk_mul;
4427 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
4429 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
4434 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
4435 host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
4437 if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
4438 host->timeout_clk *= 1000;
4440 if (host->timeout_clk == 0) {
4441 if (!host->ops->get_timeout_clock) {
4448 host->timeout_clk =
4449 DIV_ROUND_UP(host->ops->get_timeout_clock(host),
4454 host->timeout_clk = override_timeout_clk;
4456 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
4457 host->ops->get_max_timeout_count(host) : 1 << 27;
4458 mmc->max_busy_timeout /= host->timeout_clk;
4461 if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT &&
4462 !host->ops->get_max_timeout_count)
4468 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
4469 host->flags |= SDHCI_AUTO_CMD12;
4475 if ((host->version >= SDHCI_SPEC_300) &&
4476 ((host->flags & SDHCI_USE_ADMA) ||
4477 !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) &&
4478 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
4479 host->flags |= SDHCI_AUTO_CMD23;
4492 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
4495 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
4498 if (host->caps & SDHCI_CAN_DO_HISPD)
4501 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
4509 host->sdhci_core_to_disable_vqmmc = !ret;
4515 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 |
4522 host->flags &= ~SDHCI_SIGNALING_330;
4532 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) {
4533 host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4548 if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
4553 if (host->caps1 & SDHCI_SUPPORT_SDR104) {
4558 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
4560 } else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
4564 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
4565 (host->caps1 & SDHCI_SUPPORT_HS400))
4574 if ((host->caps1 & SDHCI_SUPPORT_DDR50) &&
4575 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
4578 /* Does the host need tuning for SDR50? */
4579 if (host->caps1 & SDHCI_USE_SDR50_TUNING)
4580 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
4582 /* Driver Type(s) (A, C, D) supported by the host */
4583 if (host->caps1 & SDHCI_DRIVER_TYPE_A)
4585 if (host->caps1 & SDHCI_DRIVER_TYPE_C)
4587 if (host->caps1 & SDHCI_DRIVER_TYPE_D)
4591 host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
4592 host->caps1);
4598 if (host->tuning_count)
4599 host->tuning_count = 1 << (host->tuning_count - 1);
4602 host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
4613 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
4630 if (host->caps & SDHCI_CAN_VDD_330) {
4637 if (host->caps & SDHCI_CAN_VDD_300) {
4644 if (host->caps & SDHCI_CAN_VDD_180) {
4652 /* If OCR set by host, use it instead. */
4653 if (host->ocr_mask)
4654 ocr_avail = host->ocr_mask;
4662 if (host->ocr_avail_sdio)
4663 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
4665 if (host->ocr_avail_sd)
4666 mmc->ocr_avail_sd &= host->ocr_avail_sd;
4670 if (host->ocr_avail_mmc)
4671 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
4684 host->flags |= SDHCI_SIGNALING_180;
4687 host->flags |= SDHCI_SIGNALING_120;
4689 spin_lock_init(&host->lock);
4702 if (host->flags & SDHCI_USE_ADMA) {
4704 } else if (host->flags & SDHCI_USE_SDMA) {
4717 if (host->flags & SDHCI_USE_ADMA) {
4718 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) {
4719 host->max_adma = 65532; /* 32-bit alignment */
4732 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
4735 mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >>
4749 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
4753 sdhci_allocate_bounce_buffer(host);
4758 if (host->sdhci_core_to_disable_vqmmc)
4761 if (host->align_buffer)
4762 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4763 host->adma_table_sz, host->align_buffer,
4764 host->align_addr);
4765 host->adma_table = NULL;
4766 host->align_buffer = NULL;
4772 void sdhci_cleanup_host(struct sdhci_host *host)
4774 struct mmc_host *mmc = host->mmc;
4776 if (host->sdhci_core_to_disable_vqmmc)
4779 if (host->align_buffer)
4780 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4781 host->adma_table_sz, host->align_buffer,
4782 host->align_addr);
4784 if (host->use_external_dma)
4785 sdhci_external_dma_release(host);
4787 host->adma_table = NULL;
4788 host->align_buffer = NULL;
4792 int __sdhci_add_host(struct sdhci_host *host)
4795 struct mmc_host *mmc = host->mmc;
4799 (host->quirks & SDHCI_QUIRK_BROKEN_CQE)) {
4804 host->complete_wq = alloc_workqueue("sdhci", flags, 0);
4805 if (!host->complete_wq)
4808 INIT_WORK(&host->complete_work, sdhci_complete_work);
4810 timer_setup(&host->timer, sdhci_timeout_timer, 0);
4811 timer_setup(&host->data_timer, sdhci_timeout_data_timer, 0);
4813 init_waitqueue_head(&host->buf_ready_int);
4815 sdhci_init(host, 0);
4817 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
4818 IRQF_SHARED, mmc_hostname(mmc), host);
4821 mmc_hostname(mmc), host->irq, ret);
4825 ret = sdhci_led_register(host);
4837 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
4838 host->use_external_dma ? "External DMA" :
4839 (host->flags & SDHCI_USE_ADMA) ?
4840 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
4841 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
4843 sdhci_enable_card_detection(host);
4848 sdhci_led_unregister(host);
4850 sdhci_reset_for_all(host);
4851 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4852 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4853 free_irq(host->irq, host);
4855 destroy_workqueue(host->complete_wq);
4861 int sdhci_add_host(struct sdhci_host *host)
4865 ret = sdhci_setup_host(host);
4869 ret = __sdhci_add_host(host);
4876 sdhci_cleanup_host(host);
4882 void sdhci_remove_host(struct sdhci_host *host, int dead)
4884 struct mmc_host *mmc = host->mmc;
4888 spin_lock_irqsave(&host->lock, flags);
4890 host->flags |= SDHCI_DEVICE_DEAD;
4892 if (sdhci_has_requests(host)) {
4895 sdhci_error_out_mrqs(host, -ENOMEDIUM);
4898 spin_unlock_irqrestore(&host->lock, flags);
4901 sdhci_disable_card_detection(host);
4905 sdhci_led_unregister(host);
4908 sdhci_reset_for_all(host);
4910 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
4911 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
4912 free_irq(host->irq, host);
4914 del_timer_sync(&host->timer);
4915 del_timer_sync(&host->data_timer);
4917 destroy_workqueue(host->complete_wq);
4919 if (host->sdhci_core_to_disable_vqmmc)
4922 if (host->align_buffer)
4923 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
4924 host->adma_table_sz, host->align_buffer,
4925 host->align_addr);
4927 if (host->use_external_dma)
4928 sdhci_external_dma_release(host);
4930 host->adma_table = NULL;
4931 host->align_buffer = NULL;
4936 void sdhci_free_host(struct sdhci_host *host)
4938 mmc_free_host(host->mmc);