mmc/host/sdhci-pci-gli.c

218 static inline void gl9750_wt_on(struct sdhci_host *host)
223 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
232 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
235 static inline void gl9750_wt_off(struct sdhci_host *host)
240 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
249 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
252 static void gli_set_9750(struct sdhci_host *host)
262 	gl9750_wt_on(host);
264 	driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
265 	pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
266 	sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
267 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
268 	parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
269 	control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
279 	sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
284 	sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
315 	sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
316 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
319 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
321 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
327 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
330 	sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
336 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
339 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
341 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
343 	gl9750_wt_off(host);
346 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
350 	gl9750_wt_on(host);
352 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
361 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
363 	gl9750_wt_off(host);
366 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
372 		gli_set_9750_rx_inv(host, !!rx_inv);
373 		sdhci_start_tuning(host);
378 			sdhci_send_tuning(host, opcode);
380 			if (!host->tuning_done) {
381 				sdhci_abort_tuning(host, opcode);
385 			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
393 	if (!host->tuning_done) {
395 			mmc_hostname(host->mmc));
400 		mmc_hostname(host->mmc));
401 	sdhci_reset_tuning(host);
406 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
408 	host->mmc->retune_period = 0;
409 	if (host->tuning_mode == SDHCI_TUNING_MODE_1)
410 		host->mmc->retune_period = host->tuning_count;
412 	gli_set_9750(host);
413 	host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
414 	sdhci_end_tuning(host);
419 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
423 	gl9750_wt_on(host);
424 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
426 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
427 	gl9750_wt_off(host);
430 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
434 	gl9750_wt_on(host);
435 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
442 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
443 	gl9750_wt_off(host);
449 static bool gl9750_ssc_enable(struct sdhci_host *host)
454 	gl9750_wt_on(host);
455 	misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
457 	gl9750_wt_off(host);
462 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
467 	gl9750_wt_on(host);
468 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
469 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
476 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
477 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
478 	gl9750_wt_off(host);
481 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
483 	bool enable = gl9750_ssc_enable(host);
486 	gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
487 	gl9750_set_pll(host, 0x1, 0x246, 0x0);
490 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
492 	bool enable = gl9750_ssc_enable(host);
495 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);
496 	gl9750_set_pll(host, 0x1, 0x244, 0x1);
499 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
501 	bool enable = gl9750_ssc_enable(host);
504 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);
505 	gl9750_set_pll(host, 0x1, 0x244, 0x3);
508 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
510 	struct mmc_ios *ios = &host->mmc->ios;
513 	host->mmc->actual_clock = 0;
515 	gl9750_disable_ssc_pll(host);
516 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
521 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
523 		host->mmc->actual_clock = 205000000;
524 		gl9750_set_ssc_pll_205mhz(host);
526 		gl9750_set_ssc_pll_100mhz(host);
528 		gl9750_set_ssc_pll_50mhz(host);
531 	sdhci_enable_clk(host, clk);
534 static void gl9750_hw_setting(struct sdhci_host *host)
536 	struct sdhci_pci_slot *slot = sdhci_priv(host);
543 	gl9750_wt_on(host);
545 	value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
550 	sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
564 	gl9750_wt_off(host);
575 		       mmc_hostname(slot->host->mmc), ret);
579 	slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
705 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
707 	struct sdhci_pci_slot *slot = sdhci_priv(host);
708 	struct mmc_ios *ios = &host->mmc->ios;
713 	host->mmc->actual_clock = 0;
716 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
721 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
723 		host->mmc->actual_clock = 205000000;
731 	sdhci_enable_clk(host, clk);
895 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
897 	struct sdhci_pci_slot *slot = sdhci_priv(host);
898 	struct mmc_ios *ios = &host->mmc->ios;
904 	host->mmc->actual_clock = 0;
913 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
918 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
920 		host->mmc->actual_clock = 205000000;
924 	sdhci_enable_clk(host, clk);
933 static void gli_set_9767(struct sdhci_host *host)
937 	value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
939 	sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
976 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
978 	sdhci_reset(host, mask);
979 	gli_set_9767(host);
984 	struct sdhci_host *host = mmc_priv(mmc);
985 	struct sdhci_pci_slot *slot = sdhci_priv(host);
1025 	value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1027 	sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1029 	value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1031 	sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1055 		value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1057 		sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1059 		value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1061 		sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1071 	struct sdhci_host *host = slot->host;
1073 	gl9750_hw_setting(host);
1075 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1076 	sdhci_enable_v4_mode(host);
1083 	struct sdhci_host *host = slot->host;
1087 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1088 	sdhci_enable_v4_mode(host);
1095 	struct sdhci_host *host = slot->host;
1097 	gli_set_9767(host);
1100 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1101 	host->mmc->caps2 |= MMC_CAP2_SD_EXP;
1102 	host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
1103 	sdhci_enable_v4_mode(host);
1108 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
1131 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
1150 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
1152 	sdhci_reset(host, mask);
1153 	gli_set_9750(host);
1156 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
1160 	value = readl(host->ioaddr + reg);
1170 	struct sdhci_host *host = mmc_priv(mmc);
1173 	val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
1179 	sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
1208 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
1213 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1224 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1244 	struct sdhci_host *host = mmc_priv(mmc);
1246 	sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1250 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
1255 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1258 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1265 	struct sdhci_host *host = mmc_priv(mmc);
1272 	sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1286 	struct sdhci_host *host = slot->host;
1291 	ret = sdhci_setup_host(host);
1301 	cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
1304 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1308 	ret = cqhci_init(cq_host, host->mmc, dma64);
1312 	ret = __sdhci_add_host(host);
1322 	sdhci_cleanup_host(host);
1365 	struct sdhci_host *host = slot->host;
1371 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1373 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1381 	struct sdhci_host *host = slot->host;
1384 	if (host->mmc->ios.power_mode != MMC_POWER_ON)
1387 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1391 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1395 			      1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1397 		       mmc_hostname(host->mmc));
1398 		sdhci_dumpregs(host);
1402 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1431 	ret = cqhci_resume(slot->host->mmc);
1457 	ret = cqhci_suspend(slot->host->mmc);
1461 	ret = sdhci_suspend_host(slot->host);
1468 	cqhci_resume(slot->host->mmc);
1478 	struct sdhci_host *host = slot->host;
1481 	host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1484 	host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1493 			host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1496 	host->mmc_host_ops.hs400_enhanced_strobe =
1499 	sdhci_enable_v4_mode(host);
1506 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1508 	u32 val = readl(host->ioaddr + (reg & ~3));
1515 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1517 	u32 val = readl(host->ioaddr + (reg & ~3));