mmc/host/sdhci-brcmstb.c

10 #include <linux/mmc/host.h>
46 static inline void enable_clock_gating(struct sdhci_host *host)
48 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
55 	reg = sdhci_readl(host, SDHCI_VENDOR);
57 	sdhci_writel(host, reg, SDHCI_VENDOR);
60 static void brcmstb_reset(struct sdhci_host *host, u8 mask)
62 	sdhci_and_cqhci_reset(host, mask);
65 	enable_clock_gating(host);
68 static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)
80 	reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
81 	sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);
83 	reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);
87 				       host, SDHCI_SOFTWARE_RESET);
91 		       mmc_hostname(host->mmc), (int)mask);
92 		sdhci_err_stats_inc(host, CTRL_TIMEOUT);
93 		sdhci_dumpregs(host);
97 static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)
101 		sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);
105 		brcmstb_sdhci_reset_cmd_data(host, mask);
108 	enable_clock_gating(host);
113 	struct sdhci_host *host = mmc_priv(mmc);
119 	reg = readl(host->ioaddr + SDHCI_VENDOR);
124 	writel(reg, host->ioaddr + SDHCI_VENDOR);
127 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
131 	host->mmc->actual_clock = 0;
133 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
134 	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
139 	sdhci_enable_clk(host, clk);
142 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
147 	dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
149 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
150 	/* Select Bus Speed Mode for host */
168 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
178 	struct sdhci_host *host = mmc_priv(mmc);
181 	reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
183 		sdhci_readl(host, SDHCI_BUFFER);
184 		reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
248 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
253 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
256 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
261 static int sdhci_brcmstb_add_host(struct sdhci_host *host,
269 		return sdhci_add_host(host);
271 	dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
272 	host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
273 	ret = sdhci_setup_host(host);
277 	cq_host = devm_kzalloc(mmc_dev(host->mmc),
284 	cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
287 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
289 		dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
293 	ret = cqhci_init(cq_host, host->mmc, dma64);
297 	ret = __sdhci_add_host(host);
304 	sdhci_cleanup_host(host);
316 	struct sdhci_host *host;
333 	host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
335 	if (IS_ERR(host))
336 		return PTR_ERR(host);
338 	pltfm_host = sdhci_priv(host);
353 	res = mmc_of_parse(host->mmc);
362 	    (host->mmc->caps & MMC_CAP_NONREMOVABLE))
370 	    (host->mmc->caps2 & MMC_CAP2_HS400_ES))
371 		host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
378 	sdhci_read_caps(host);
380 		host->caps &= ~SDHCI_CAN_64BIT;
381 	host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
385 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
406 	host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
407 	host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);
409 	host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
416 	res = sdhci_brcmstb_add_host(host, priv);
439 	struct sdhci_host *host = dev_get_drvdata(dev);
440 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
449 	struct sdhci_host *host = dev_get_drvdata(dev);
450 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);