Lines Matching refs:host
2 * drivers/mmc/host/omap_hsmmc.c
34 #include <linux/mmc/host.h>
153 #define mmc_pdata(host) host->pdata
214 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
235 host->vqmmc_enabled = true;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
259 host->vqmmc_enabled = false;
280 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
284 if (IS_ERR(host->pbias))
288 if (!host->pbias_enabled) {
289 ret = regulator_enable(host->pbias);
291 dev_err(host->dev, "pbias reg enable fail\n");
294 host->pbias_enabled = true;
297 if (host->pbias_enabled) {
298 ret = regulator_disable(host->pbias);
300 dev_err(host->dev, "pbias reg disable fail\n");
303 host->pbias_enabled = false;
310 static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
312 struct mmc_host *mmc = host->mmc;
322 ret = omap_hsmmc_set_pbias(host, false);
344 ret = omap_hsmmc_set_pbias(host, true);
381 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
383 struct mmc_host *mmc = host->mmc;
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
399 dev_err(host->dev,
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
406 dev_err(host->dev,
414 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
417 struct mmc_host *mmc = host->mmc;
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
430 if ((ret != -ENODEV) && host->dev->of_node)
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
441 dev_err(host->dev,
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
450 if (mmc_pdata(host)->no_regulator_off_init)
453 ret = omap_hsmmc_disable_boot_regulators(host);
463 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
472 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
480 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
486 if (host->use_dma)
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
504 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
509 spin_lock_irqsave(&host->irq_lock, flags);
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
520 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
533 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
535 struct mmc_ios *ios = &host->mmc->ios;
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
542 omap_hsmmc_stop_clock(host);
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
546 clkdiv = calc_divisor(host, ios);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
580 omap_hsmmc_start_clock(host);
583 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
585 struct mmc_ios *ios = &host->mmc->ios;
588 con = OMAP_HSMMC_READ(host->base, CON);
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
611 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
613 struct mmc_ios *ios = &host->mmc->ios;
616 con = OMAP_HSMMC_READ(host->base, CON);
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
626 * Restore the MMC host context, if it was lost as result of a
629 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
631 struct mmc_ios *ios = &host->mmc->ios;
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
641 host->context_loss++;
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
677 if (host->power_mode == MMC_POWER_OFF)
680 omap_hsmmc_set_bus_width(host);
682 omap_hsmmc_set_clock(host);
684 omap_hsmmc_set_bus_mode(host);
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
688 host->context_loss);
693 * Save the MMC host context (store the number of power state changes so far).
695 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
705 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
715 static void send_init_stream(struct omap_hsmmc_host *host)
720 disable_irq(host->irq);
722 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
723 OMAP_HSMMC_WRITE(host->base, CON,
724 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
725 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
729 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
731 OMAP_HSMMC_WRITE(host->base, CON,
732 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
734 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
735 OMAP_HSMMC_READ(host->base, STAT);
737 enable_irq(host->irq);
745 struct omap_hsmmc_host *host = mmc_priv(mmc);
747 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
756 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
761 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
762 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
763 host->cmd = cmd;
765 omap_hsmmc_enable_irq(host, cmd);
767 host->response_busy = 0;
773 host->response_busy = 1;
783 if (cmd == host->mrq->stop)
788 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
789 host->mrq->sbc) {
791 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
801 if (host->use_dma)
804 host->req_in_progress = 1;
806 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
807 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
810 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
813 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
816 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
821 spin_lock_irqsave(&host->irq_lock, flags);
822 host->req_in_progress = 0;
823 dma_ch = host->dma_ch;
824 spin_unlock_irqrestore(&host->irq_lock, flags);
826 omap_hsmmc_disable_irq(host);
828 if (mrq->data && host->use_dma && dma_ch != -1)
830 host->mrq = NULL;
831 mmc_request_done(host->mmc, mrq);
838 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
841 struct mmc_request *mrq = host->mrq;
844 if (host->cmd && host->cmd->opcode == 6 &&
845 host->response_busy) {
846 host->response_busy = 0;
850 omap_hsmmc_request_done(host, mrq);
854 host->data = NULL;
861 if (data->stop && (data->error || !host->mrq->sbc))
862 omap_hsmmc_start_command(host, data->stop, NULL);
864 omap_hsmmc_request_done(host, data->mrq);
871 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
873 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
874 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
875 host->cmd = NULL;
876 omap_hsmmc_start_dma_transfer(host);
877 omap_hsmmc_start_command(host, host->mrq->cmd,
878 host->mrq->data);
882 host->cmd = NULL;
887 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
888 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
889 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
890 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
893 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
896 if ((host->data == NULL && !host->response_busy) || cmd->error)
897 omap_hsmmc_request_done(host, host->mrq);
903 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
908 host->data->error = errno;
910 spin_lock_irqsave(&host->irq_lock, flags);
911 dma_ch = host->dma_ch;
912 host->dma_ch = -1;
913 spin_unlock_irqrestore(&host->irq_lock, flags);
915 if (host->use_dma && dma_ch != -1) {
916 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
920 host->data->sg, host->data->sg_len,
921 mmc_get_dma_dir(host->data));
923 host->data->host_cookie = 0;
925 host->data = NULL;
932 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
954 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
957 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
970 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
976 OMAP_HSMMC_WRITE(host->base, SYSCTL,
977 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
983 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
984 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
990 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
994 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
995 dev_err(mmc_dev(host->mmc),
1000 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1004 omap_hsmmc_reset_controller_fsm(host, SRC);
1005 if (host->cmd)
1006 host->cmd->error = err;
1009 if (host->data) {
1010 omap_hsmmc_reset_controller_fsm(host, SRD);
1011 omap_hsmmc_dma_cleanup(host, err);
1012 } else if (host->mrq && host->mrq->cmd)
1013 host->mrq->cmd->error = err;
1016 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1022 data = host->data;
1023 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1026 omap_hsmmc_dbg_report_irq(host, status);
1030 if (host->data || host->response_busy) {
1032 host->response_busy = 0;
1035 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1038 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1042 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1043 if (!(ac12 & ACNE) && host->mrq->sbc) {
1049 host->mrq->sbc->error = error;
1050 hsmmc_command_incomplete(host, error, end_cmd);
1052 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1056 OMAP_HSMMC_WRITE(host->base, STAT, status);
1057 if (end_cmd || ((status & CC_EN) && host->cmd))
1058 omap_hsmmc_cmd_done(host, host->cmd);
1059 if ((end_trans || (status & TC_EN)) && host->mrq)
1060 omap_hsmmc_xfer_done(host, data);
1068 struct omap_hsmmc_host *host = dev_id;
1071 status = OMAP_HSMMC_READ(host->base, STAT);
1073 if (host->req_in_progress)
1074 omap_hsmmc_do_irq(host, status);
1077 mmc_signal_sdio_irq(host->mmc);
1080 status = OMAP_HSMMC_READ(host->base, STAT);
1086 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1090 OMAP_HSMMC_WRITE(host->base, HCTL,
1091 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1093 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1106 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1112 clk_disable_unprepare(host->dbclk);
1115 ret = omap_hsmmc_set_power(host, 0);
1119 ret = omap_hsmmc_set_power(host, 1);
1120 clk_prepare_enable(host->dbclk);
1125 OMAP_HSMMC_WRITE(host->base, HCTL,
1126 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1127 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1149 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1150 set_sd_bus_power(host);
1154 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1160 struct omap_hsmmc_host *host = param;
1165 spin_lock_irq(&host->irq_lock);
1166 if (host->dma_ch < 0) {
1167 spin_unlock_irq(&host->irq_lock);
1171 data = host->mrq->data;
1172 chan = omap_hsmmc_get_dma_chan(host, data);
1178 req_in_progress = host->req_in_progress;
1179 host->dma_ch = -1;
1180 spin_unlock_irq(&host->irq_lock);
1184 struct mmc_request *mrq = host->mrq;
1186 host->mrq = NULL;
1187 mmc_request_done(host->mmc, mrq);
1191 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1199 data->host_cookie != host->next_data.cookie) {
1200 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1201 " host->next_data.cookie %d\n",
1202 __func__, data->host_cookie, host->next_data.cookie);
1207 if (next || data->host_cookie != host->next_data.cookie) {
1212 dma_len = host->next_data.dma_len;
1213 host->next_data.dma_len = 0;
1224 host->dma_len = dma_len;
1232 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1240 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1241 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1262 BUG_ON(host->dma_ch != -1);
1264 chan = omap_hsmmc_get_dma_chan(host, data);
1270 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1278 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1284 tx->callback_param = host;
1289 host->dma_ch = 1;
1294 static void set_data_timeout(struct omap_hsmmc_host *host,
1302 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1307 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1329 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1332 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1334 struct mmc_request *req = host->mrq;
1339 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1341 set_data_timeout(host, req->data->timeout_ns,
1343 chan = omap_hsmmc_get_dma_chan(host, req->data);
1351 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1356 host->data = req->data;
1359 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1370 set_data_timeout(host, timeout, 0);
1375 if (host->use_dma) {
1376 ret = omap_hsmmc_setup_dma_transfer(host, req);
1378 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1388 struct omap_hsmmc_host *host = mmc_priv(mmc);
1391 if (host->use_dma && data->host_cookie) {
1392 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1402 struct omap_hsmmc_host *host = mmc_priv(mmc);
1409 if (host->use_dma) {
1410 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1412 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1413 &host->next_data, c))
1423 struct omap_hsmmc_host *host = mmc_priv(mmc);
1426 BUG_ON(host->req_in_progress);
1427 BUG_ON(host->dma_ch != -1);
1428 if (host->reqs_blocked)
1429 host->reqs_blocked = 0;
1430 WARN_ON(host->mrq != NULL);
1431 host->mrq = req;
1432 host->clk_rate = clk_get_rate(host->fclk);
1433 err = omap_hsmmc_prepare_data(host, req);
1438 host->mrq = NULL;
1442 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1443 omap_hsmmc_start_command(host, req->sbc, NULL);
1447 omap_hsmmc_start_dma_transfer(host);
1448 omap_hsmmc_start_command(host, req->cmd, req->data);
1454 struct omap_hsmmc_host *host = mmc_priv(mmc);
1457 if (ios->power_mode != host->power_mode) {
1460 omap_hsmmc_set_power(host, 0);
1463 omap_hsmmc_set_power(host, 1);
1469 host->power_mode = ios->power_mode;
1474 omap_hsmmc_set_bus_width(host);
1476 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1480 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1488 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1489 dev_dbg(mmc_dev(host->mmc),
1494 omap_hsmmc_set_clock(host);
1497 send_init_stream(host);
1499 omap_hsmmc_set_bus_mode(host);
1504 struct omap_hsmmc_host *host = mmc_priv(mmc);
1508 spin_lock_irqsave(&host->irq_lock, flags);
1510 con = OMAP_HSMMC_READ(host->base, CON);
1511 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1513 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1517 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1521 OMAP_HSMMC_WRITE(host->base, CON, con);
1522 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1528 if (!host->req_in_progress || !enable)
1529 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1532 OMAP_HSMMC_READ(host->base, IE);
1534 spin_unlock_irqrestore(&host->irq_lock, flags);
1537 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1547 if (!host->dev->of_node || !host->wake_irq)
1550 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1552 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1560 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1561 struct pinctrl *p = devm_pinctrl_get(host->dev);
1568 dev_info(host->dev, "missing idle pinctrl state\n");
1576 OMAP_HSMMC_WRITE(host->base, HCTL,
1577 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1581 dev_pm_clear_wake_irq(host->dev);
1583 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1584 host->wake_irq = 0;
1588 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1593 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1601 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1602 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1604 value = OMAP_HSMMC_READ(host->base, CAPA);
1605 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1608 set_sd_bus_power(host);
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1644 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1647 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1649 pm_runtime_get_sync(host->dev);
1652 OMAP_HSMMC_READ(host->base, CON));
1654 OMAP_HSMMC_READ(host->base, PSTATE));
1656 OMAP_HSMMC_READ(host->base, HCTL));
1658 OMAP_HSMMC_READ(host->base, SYSCTL));
1660 OMAP_HSMMC_READ(host->base, IE));
1662 OMAP_HSMMC_READ(host->base, ISE));
1664 OMAP_HSMMC_READ(host->base, CAPA));
1666 pm_runtime_mark_last_busy(host->dev);
1667 pm_runtime_put_autosuspend(host->dev);
1767 struct omap_hsmmc_host *host = NULL;
1811 host = mmc_priv(mmc);
1812 host->mmc = mmc;
1813 host->pdata = pdata;
1814 host->dev = &pdev->dev;
1815 host->use_dma = 1;
1816 host->dma_ch = -1;
1817 host->irq = irq;
1818 host->mapbase = res->start + pdata->reg_offset;
1819 host->base = base + pdata->reg_offset;
1820 host->power_mode = MMC_POWER_OFF;
1821 host->next_data.cookie = 1;
1822 host->pbias_enabled = false;
1823 host->vqmmc_enabled = false;
1825 platform_set_drvdata(pdev, host);
1828 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1839 spin_lock_init(&host->irq_lock);
1841 host->fclk = devm_clk_get(&pdev->dev, "fck");
1842 if (IS_ERR(host->fclk)) {
1843 ret = PTR_ERR(host->fclk);
1844 host->fclk = NULL;
1848 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1854 pm_runtime_enable(host->dev);
1855 pm_runtime_get_sync(host->dev);
1856 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1857 pm_runtime_use_autosuspend(host->dev);
1859 omap_hsmmc_context_save(host);
1861 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1865 if (IS_ERR(host->dbclk)) {
1866 host->dbclk = NULL;
1867 } else if (clk_prepare_enable(host->dbclk) != 0) {
1868 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1869 host->dbclk = NULL;
1883 mmc->caps |= mmc_pdata(host)->caps;
1887 if (mmc_pdata(host)->nonremovable)
1890 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1892 omap_hsmmc_conf_bus_power(host);
1894 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1895 if (IS_ERR(host->rx_chan)) {
1896 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1897 ret = PTR_ERR(host->rx_chan);
1901 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1902 if (IS_ERR(host->tx_chan)) {
1903 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1904 ret = PTR_ERR(host->tx_chan);
1916 dma_get_max_seg_size(host->rx_chan->device->dev),
1917 dma_get_max_seg_size(host->tx_chan->device->dev));
1920 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1921 mmc_hostname(mmc), host);
1923 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1927 ret = omap_hsmmc_reg_get(host);
1932 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1934 omap_hsmmc_disable_irq(host);
1944 ret = omap_hsmmc_configure_wake_irq(host);
1952 if (mmc_pdata(host)->name != NULL) {
1959 pm_runtime_mark_last_busy(host->dev);
1960 pm_runtime_put_autosuspend(host->dev);
1968 if (!IS_ERR_OR_NULL(host->tx_chan))
1969 dma_release_channel(host->tx_chan);
1970 if (!IS_ERR_OR_NULL(host->rx_chan))
1971 dma_release_channel(host->rx_chan);
1972 pm_runtime_dont_use_autosuspend(host->dev);
1973 pm_runtime_put_sync(host->dev);
1974 pm_runtime_disable(host->dev);
1975 clk_disable_unprepare(host->dbclk);
1984 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1986 pm_runtime_get_sync(host->dev);
1987 mmc_remove_host(host->mmc);
1989 dma_release_channel(host->tx_chan);
1990 dma_release_channel(host->rx_chan);
1992 dev_pm_clear_wake_irq(host->dev);
1993 pm_runtime_dont_use_autosuspend(host->dev);
1994 pm_runtime_put_sync(host->dev);
1995 pm_runtime_disable(host->dev);
1997 clk_disable_unprepare(host->dbclk);
1999 mmc_free_host(host->mmc);
2005 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2007 if (!host)
2010 pm_runtime_get_sync(host->dev);
2012 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2013 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2014 OMAP_HSMMC_WRITE(host->base, IE, 0);
2015 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2016 OMAP_HSMMC_WRITE(host->base, HCTL,
2017 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2020 clk_disable_unprepare(host->dbclk);
2022 pm_runtime_put_sync(host->dev);
2029 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2031 if (!host)
2034 pm_runtime_get_sync(host->dev);
2036 clk_prepare_enable(host->dbclk);
2038 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2039 omap_hsmmc_conf_bus_power(host);
2041 pm_runtime_mark_last_busy(host->dev);
2042 pm_runtime_put_autosuspend(host->dev);
2050 struct omap_hsmmc_host *host;
2054 host = dev_get_drvdata(dev);
2055 omap_hsmmc_context_save(host);
2058 spin_lock_irqsave(&host->irq_lock, flags);
2059 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2060 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2062 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2063 OMAP_HSMMC_WRITE(host->base, IE, 0);
2065 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2072 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2073 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2074 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2086 spin_unlock_irqrestore(&host->irq_lock, flags);
2092 struct omap_hsmmc_host *host;
2095 host = dev_get_drvdata(dev);
2096 omap_hsmmc_context_restore(host);
2099 spin_lock_irqsave(&host->irq_lock, flags);
2100 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2101 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2103 pinctrl_select_default_state(host->dev);
2106 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2107 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2108 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2110 pinctrl_select_default_state(host->dev);
2112 spin_unlock_irqrestore(&host->irq_lock, flags);