mmc/host/mxs-mmc.c

48 	struct mxs_ssp			ssp;
64 	struct mxs_ssp *ssp = &host->ssp;
75 		!(readl(ssp->base + HW_SSP_STATUS(ssp)) &
86 	struct mxs_ssp *ssp = &host->ssp;
90 	ret = stmp_reset_block(ssp->base);
108 	       ssp->base + HW_SSP_TIMING(ssp));
115 	writel(ctrl0, ssp->base + HW_SSP_CTRL0);
116 	writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
128 	struct mxs_ssp *ssp = &host->ssp;
132 			cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
133 			cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
134 			cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
135 			cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
137 			cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
147 			     data->sg_len, ssp->dma_dir);
180 	struct mxs_ssp *ssp = &host->ssp;
185 	stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
187 	       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
216 	struct mxs_ssp *ssp = &host->ssp;
225 			   data->sg_len, ssp->dma_dir);
230 		sgl = (struct scatterlist *) ssp->ssp_pio_words;
234 	desc = dmaengine_prep_slave_sg(ssp->dmach,
235 				sgl, sg_len, ssp->slave_dirn, flags);
242 				     data->sg_len, ssp->dma_dir);
250 	struct mxs_ssp *ssp = &host->ssp;
264 	ssp->ssp_pio_words[0] = ctrl0;
265 	ssp->ssp_pio_words[1] = cmd0;
266 	ssp->ssp_pio_words[2] = cmd1;
267 	ssp->dma_dir = DMA_NONE;
268 	ssp->slave_dirn = DMA_TRANS_NONE;
274 	dma_async_issue_pending(ssp->dmach);
284 	struct mxs_ssp *ssp = &host->ssp;
309 	ssp->ssp_pio_words[0] = ctrl0;
310 	ssp->ssp_pio_words[1] = cmd0;
311 	ssp->ssp_pio_words[2] = cmd1;
312 	ssp->dma_dir = DMA_NONE;
313 	ssp->slave_dirn = DMA_TRANS_NONE;
319 	dma_async_issue_pending(ssp->dmach);
357 	struct mxs_ssp *ssp = &host->ssp;
401 	if (ssp_is_old(ssp)) {
406 		writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
409 		       ssp->base + HW_SSP_BLOCK_SIZE);
423 	timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
424 	val = readl(ssp->base + HW_SSP_TIMING(ssp));
427 	writel(val, ssp->base + HW_SSP_TIMING(ssp));
430 	ssp->ssp_pio_words[0] = ctrl0;
431 	ssp->ssp_pio_words[1] = cmd0;
432 	ssp->ssp_pio_words[2] = cmd1;
433 	ssp->dma_dir = DMA_NONE;
434 	ssp->slave_dirn = DMA_TRANS_NONE;
442 	ssp->dma_dir = dma_data_dir;
443 	ssp->slave_dirn = slave_dirn;
449 	dma_async_issue_pending(ssp->dmach);
506 		mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
512 	struct mxs_ssp *ssp = &host->ssp;
521 		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
523 		       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
526 		       ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
528 		       ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
533 	if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
566 	struct mxs_ssp *ssp;
577 	ssp = &host->ssp;
578 	ssp->dev = &pdev->dev;
579 	ssp->base = devm_platform_ioremap_resource(pdev, 0);
580 	if (IS_ERR(ssp->base)) {
581 		ret = PTR_ERR(ssp->base);
585 	ssp->devid = (enum mxs_ssp_id)of_device_get_match_data(&pdev->dev);
605 	ssp->clk = devm_clk_get(&pdev->dev, NULL);
606 	if (IS_ERR(ssp->clk)) {
607 		ret = PTR_ERR(ssp->clk);
610 	ret = clk_prepare_enable(ssp->clk);
620 	ssp->dmach = dma_request_chan(&pdev->dev, "rx-tx");
621 	if (IS_ERR(ssp->dmach)) {
624 		ret = PTR_ERR(ssp->dmach);
646 	mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
647 	mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
648 	mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
668 	dma_release_channel(ssp->dmach);
670 	clk_disable_unprepare(ssp->clk);
680 	struct mxs_ssp *ssp = &host->ssp;
684 	if (ssp->dmach)
685 		dma_release_channel(ssp->dmach);
687 	clk_disable_unprepare(ssp->clk);
697 	struct mxs_ssp *ssp = &host->ssp;
699 	clk_disable_unprepare(ssp->clk);
707 	struct mxs_ssp *ssp = &host->ssp;
709 	return clk_prepare_enable(ssp->clk);