Lines Matching defs:host
29 #include <linux/mmc/host.h>
435 void __iomem *base; /* host base address */
436 void __iomem *top_base; /* host top register base address */
449 int irq; /* host interrupt */
673 static void msdc_reset_hw(struct msdc_host *host)
677 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
678 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
680 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
681 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
684 val = readl(host->base + MSDC_INT);
685 writel(val, host->base + MSDC_INT);
688 static void msdc_cmd_next(struct msdc_host *host,
690 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
708 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
739 if (host->dev_comp->support_64g) {
745 if (host->dev_comp->support_64g) {
763 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
764 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
767 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
768 if (host->dev_comp->support_64g)
769 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
771 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
774 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
778 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
783 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
789 dma_unmap_sg(host->dev, data->sg, data->sg_len,
795 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
797 struct mmc_host *mmc = mmc_from_priv(host);
811 if (host->dev_comp->clk_div_bits == 8)
812 sdr_get_field(host->base + MSDC_CFG,
815 sdr_get_field(host->base + MSDC_CFG,
825 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
829 host->timeout_ns = ns;
830 host->timeout_clks = clks;
832 timeout = msdc_timeout_cal(host, ns, clks);
833 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
837 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
841 timeout = msdc_timeout_cal(host, ns, clks);
842 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
846 static void msdc_gate_clock(struct msdc_host *host)
848 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
849 clk_disable_unprepare(host->crypto_clk);
850 clk_disable_unprepare(host->src_clk_cg);
851 clk_disable_unprepare(host->src_clk);
852 clk_disable_unprepare(host->bus_clk);
853 clk_disable_unprepare(host->h_clk);
856 static int msdc_ungate_clock(struct msdc_host *host)
861 clk_prepare_enable(host->h_clk);
862 clk_prepare_enable(host->bus_clk);
863 clk_prepare_enable(host->src_clk);
864 clk_prepare_enable(host->src_clk_cg);
865 clk_prepare_enable(host->crypto_clk);
866 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
868 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
872 return readl_poll_timeout(host->base + MSDC_CFG, val,
876 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
878 struct mmc_host *mmc = mmc_from_priv(host);
883 u32 tune_reg = host->dev_comp->pad_tune_reg;
887 dev_dbg(host->dev, "set mclk to 0\n");
888 host->mclk = 0;
890 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
894 flags = readl(host->base + MSDC_INTEN);
895 sdr_clr_bits(host->base + MSDC_INTEN, flags);
896 if (host->dev_comp->clk_div_bits == 8)
897 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
899 sdr_clr_bits(host->base + MSDC_CFG,
909 if (hz >= (host->src_clk_freq >> 2)) {
911 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
913 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
914 sclk = (host->src_clk_freq >> 2) / div;
919 hz >= (host->src_clk_freq >> 1)) {
920 if (host->dev_comp->clk_div_bits == 8)
921 sdr_set_bits(host->base + MSDC_CFG,
924 sdr_set_bits(host->base + MSDC_CFG,
926 sclk = host->src_clk_freq >> 1;
929 } else if (hz >= host->src_clk_freq) {
932 sclk = host->src_clk_freq;
935 if (hz >= (host->src_clk_freq >> 1)) {
937 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
939 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
940 sclk = (host->src_clk_freq >> 2) / div;
943 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
945 clk_disable_unprepare(host->src_clk_cg);
946 if (host->dev_comp->clk_div_bits == 8)
947 sdr_set_field(host->base + MSDC_CFG,
951 sdr_set_field(host->base + MSDC_CFG,
955 clk_prepare_enable(host->src_clk_cg);
956 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
957 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
959 host->mclk = hz;
960 host->timing = timing;
962 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
963 sdr_set_bits(host->base + MSDC_INTEN, flags);
970 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
971 if (host->top_base) {
972 writel(host->def_tune_para.emmc_top_control,
973 host->top_base + EMMC_TOP_CONTROL);
974 writel(host->def_tune_para.emmc_top_cmd,
975 host->top_base + EMMC_TOP_CMD);
977 writel(host->def_tune_para.pad_tune,
978 host->base + tune_reg);
981 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
982 writel(host->saved_tune_para.pad_cmd_tune,
983 host->base + PAD_CMD_TUNE);
984 if (host->top_base) {
985 writel(host->saved_tune_para.emmc_top_control,
986 host->top_base + EMMC_TOP_CONTROL);
987 writel(host->saved_tune_para.emmc_top_cmd,
988 host->top_base + EMMC_TOP_CMD);
990 writel(host->saved_tune_para.pad_tune,
991 host->base + tune_reg);
996 host->dev_comp->hs400_tune)
997 sdr_set_field(host->base + tune_reg,
999 host->hs400_cmd_int_delay);
1000 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1004 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1032 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1035 struct mmc_host *mmc = mmc_from_priv(host);
1041 u32 resp = msdc_cmd_find_resp(host, cmd);
1044 host->cmd_rsp = resp;
1075 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1077 if (host->timeout_ns != data->timeout_ns ||
1078 host->timeout_clks != data->timeout_clks)
1079 msdc_set_timeout(host, data->timeout_ns,
1082 writel(data->blocks, host->base + SDC_BLK_NUM);
1087 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1092 WARN_ON(host->data);
1093 host->data = data;
1096 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1097 msdc_dma_setup(host, &host->dma, data);
1098 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1099 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1100 dev_dbg(host->dev, "DMA start\n");
1101 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1105 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1110 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1115 msdc_reset_hw(host);
1118 host->error |= REQ_STOP_EIO;
1121 host->error |= REQ_STOP_TMO;
1123 dev_err(host->dev,
1137 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1139 struct mmc_host *mmc = mmc_from_priv(host);
1143 reg_inten = readl(host->base + MSDC_INTEN);
1145 reg_int = readl(host->base + MSDC_INT);
1146 reg_ps = readl(host->base + MSDC_PS);
1149 __msdc_enable_sdio_irq(host, 0);
1156 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1158 if (host->error &&
1159 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1161 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1162 __func__, cmd->opcode, cmd->arg, host->error);
1165 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1173 cancel_delayed_work(&host->req_timeout);
1175 spin_lock_irqsave(&host->lock, flags);
1176 host->mrq = NULL;
1177 spin_unlock_irqrestore(&host->lock, flags);
1179 msdc_track_cmd_data(host, mrq->cmd);
1181 msdc_unprepare_data(host, mrq->data);
1182 if (host->error)
1183 msdc_reset_hw(host);
1184 mmc_request_done(mmc_from_priv(host), mrq);
1185 if (host->dev_comp->recheck_sdio_irq)
1186 msdc_recheck_sdio_irq(host);
1190 static bool msdc_cmd_done(struct msdc_host *host, int events,
1201 msdc_auto_cmd_done(host, events, mrq->sbc);
1210 spin_lock_irqsave(&host->lock, flags);
1211 done = !host->cmd;
1212 host->cmd = NULL;
1213 spin_unlock_irqrestore(&host->lock, flags);
1219 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1223 rsp[0] = readl(host->base + SDC_RESP3);
1224 rsp[1] = readl(host->base + SDC_RESP2);
1225 rsp[2] = readl(host->base + SDC_RESP1);
1226 rsp[3] = readl(host->base + SDC_RESP0);
1228 rsp[0] = readl(host->base + SDC_RESP0);
1234 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1240 msdc_reset_hw(host);
1243 host->error |= REQ_CMD_EIO;
1246 host->error |= REQ_CMD_TMO;
1250 dev_dbg(host->dev,
1255 msdc_cmd_next(host, mrq, cmd);
1260 * is correct before issue a request. but host design do below
1263 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1270 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1273 dev_err(host->dev, "CMD bus busy detected\n");
1274 host->error |= REQ_CMD_BUSY;
1275 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1281 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1284 dev_err(host->dev, "Controller busy detected\n");
1285 host->error |= REQ_CMD_BUSY;
1286 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1293 static void msdc_start_command(struct msdc_host *host,
1299 WARN_ON(host->cmd);
1300 host->cmd = cmd;
1302 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1303 if (!msdc_cmd_is_ready(host, mrq, cmd))
1306 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1307 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1308 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1309 msdc_reset_hw(host);
1313 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1315 spin_lock_irqsave(&host->lock, flags);
1316 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1317 spin_unlock_irqrestore(&host->lock, flags);
1319 writel(cmd->arg, host->base + SDC_ARG);
1320 writel(rawcmd, host->base + SDC_CMD);
1323 static void msdc_cmd_next(struct msdc_host *host,
1328 (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) ||
1330 msdc_request_done(host, mrq);
1332 msdc_start_command(host, mrq, mrq->cmd);
1334 msdc_request_done(host, mrq);
1336 msdc_start_data(host, cmd, cmd->data);
1341 struct msdc_host *host = mmc_priv(mmc);
1343 host->error = 0;
1344 WARN_ON(host->mrq);
1345 host->mrq = mrq;
1348 msdc_prepare_data(host, mrq->data);
1356 msdc_start_command(host, mrq, mrq->sbc);
1358 msdc_start_command(host, mrq, mrq->cmd);
1363 struct msdc_host *host = mmc_priv(mmc);
1369 msdc_prepare_data(host, data);
1376 struct msdc_host *host = mmc_priv(mmc);
1384 msdc_unprepare_data(host, data);
1388 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1392 msdc_start_command(host, mrq, mrq->stop);
1394 msdc_request_done(host, mrq);
1397 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1410 spin_lock_irqsave(&host->lock, flags);
1411 done = !host->data;
1413 host->data = NULL;
1414 spin_unlock_irqrestore(&host->lock, flags);
1421 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1422 readl(host->base + MSDC_DMA_CFG));
1423 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1426 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1429 dev_dbg(host->dev, "DMA stop timed out\n");
1431 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1434 dev_dbg(host->dev, "DMA inactive timed out\n");
1436 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1437 dev_dbg(host->dev, "DMA stop\n");
1442 dev_dbg(host->dev, "interrupt events: %x\n", events);
1443 msdc_reset_hw(host);
1444 host->error |= REQ_DAT_ERR;
1452 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1454 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1458 msdc_data_xfer_next(host, mrq);
1462 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1464 u32 val = readl(host->base + SDC_CFG);
1481 writel(val, host->base + SDC_CFG);
1482 dev_dbg(host->dev, "Bus Width = %d", width);
1487 struct msdc_host *host = mmc_priv(mmc);
1493 dev_err(host->dev, "Unsupported signal voltage!\n");
1499 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1506 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1508 pinctrl_select_state(host->pinctrl, host->pins_default);
1515 struct msdc_host *host = mmc_priv(mmc);
1516 u32 status = readl(host->base + MSDC_PS);
1524 struct msdc_host *host = container_of(work, struct msdc_host,
1528 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1529 if (host->mrq) {
1530 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1531 host->mrq, host->mrq->cmd->opcode);
1532 if (host->cmd) {
1533 dev_err(host->dev, "%s: aborting cmd=%d\n",
1534 __func__, host->cmd->opcode);
1535 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1536 host->cmd);
1537 } else if (host->data) {
1538 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1539 __func__, host->mrq->cmd->opcode,
1540 host->data->blocks);
1541 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1542 host->data);
1547 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1550 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1551 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1552 if (host->dev_comp->recheck_sdio_irq)
1553 msdc_recheck_sdio_irq(host);
1555 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1556 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1562 struct msdc_host *host = mmc_priv(mmc);
1566 spin_lock_irqsave(&host->lock, flags);
1567 __msdc_enable_sdio_irq(host, enb);
1568 spin_unlock_irqrestore(&host->lock, flags);
1570 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1578 pinctrl_select_state(host->pinctrl, host->pins_eint);
1579 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1582 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1583 host->pins_eint = NULL;
1584 pm_runtime_get_noresume(host->dev);
1586 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1589 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1591 dev_pm_clear_wake_irq(host->dev);
1595 /* Ensure host->pins_eint is NULL */
1596 host->pins_eint = NULL;
1597 pm_runtime_get_noresume(host->dev);
1599 pm_runtime_put_noidle(host->dev);
1604 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1606 struct mmc_host *mmc = mmc_from_priv(host);
1611 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1614 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1619 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1622 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1626 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1635 struct msdc_host *host = (struct msdc_host *) dev_id;
1636 struct mmc_host *mmc = mmc_from_priv(host);
1644 spin_lock(&host->lock);
1645 events = readl(host->base + MSDC_INT);
1646 event_mask = readl(host->base + MSDC_INTEN);
1648 __msdc_enable_sdio_irq(host, 0);
1650 writel(events & event_mask, host->base + MSDC_INT);
1652 mrq = host->mrq;
1653 cmd = host->cmd;
1654 data = host->data;
1655 spin_unlock(&host->lock);
1661 if (host->internal_cd)
1671 msdc_cmdq_irq(host, events);
1673 writel(events, host->base + MSDC_INT);
1678 dev_err(host->dev,
1685 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1688 msdc_cmd_done(host, events, mrq, cmd);
1690 msdc_data_xfer_done(host, events, mrq, data);
1696 static void msdc_init_hw(struct msdc_host *host)
1699 u32 tune_reg = host->dev_comp->pad_tune_reg;
1700 struct mmc_host *mmc = mmc_from_priv(host);
1702 if (host->reset) {
1703 reset_control_assert(host->reset);
1705 reset_control_deassert(host->reset);
1709 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1712 msdc_reset_hw(host);
1715 writel(0, host->base + MSDC_INTEN);
1716 val = readl(host->base + MSDC_INT);
1717 writel(val, host->base + MSDC_INT);
1720 if (host->internal_cd) {
1721 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1723 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1724 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1725 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1727 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1728 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1729 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1732 if (host->top_base) {
1733 writel(0, host->top_base + EMMC_TOP_CONTROL);
1734 writel(0, host->top_base + EMMC_TOP_CMD);
1736 writel(0, host->base + tune_reg);
1738 writel(0, host->base + MSDC_IOCON);
1739 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1740 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1741 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1742 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1743 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1745 if (host->dev_comp->stop_clk_fix) {
1746 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1748 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1750 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1754 if (host->dev_comp->busy_check)
1755 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1757 if (host->dev_comp->async_fifo) {
1758 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1760 if (host->dev_comp->enhance_rx) {
1761 if (host->top_base)
1762 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1765 sdr_set_bits(host->base + SDC_ADV_CFG0,
1768 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1770 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1774 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1776 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1780 if (host->dev_comp->support_64g)
1781 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1783 if (host->dev_comp->data_tune) {
1784 if (host->top_base) {
1785 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1787 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1789 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1791 if (host->tuning_step > PAD_DELAY_HALF) {
1792 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1794 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1798 sdr_set_bits(host->base + tune_reg,
1801 if (host->tuning_step > PAD_DELAY_HALF)
1802 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
1808 if (host->top_base)
1809 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1812 sdr_set_bits(host->base + tune_reg,
1817 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1818 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1819 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1822 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1825 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1826 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1830 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1832 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1833 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1834 if (host->top_base) {
1835 host->def_tune_para.emmc_top_control =
1836 readl(host->top_base + EMMC_TOP_CONTROL);
1837 host->def_tune_para.emmc_top_cmd =
1838 readl(host->top_base + EMMC_TOP_CMD);
1839 host->saved_tune_para.emmc_top_control =
1840 readl(host->top_base + EMMC_TOP_CONTROL);
1841 host->saved_tune_para.emmc_top_cmd =
1842 readl(host->top_base + EMMC_TOP_CMD);
1844 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1845 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1847 dev_dbg(host->dev, "init hardware done!");
1850 static void msdc_deinit_hw(struct msdc_host *host)
1854 if (host->internal_cd) {
1856 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1857 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1861 writel(0, host->base + MSDC_INTEN);
1863 val = readl(host->base + MSDC_INT);
1864 writel(val, host->base + MSDC_INT);
1868 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1883 if (host->dev_comp->support_64g)
1888 if (host->dev_comp->support_64g)
1895 if (host->dev_comp->support_64g)
1902 struct msdc_host *host = mmc_priv(mmc);
1905 msdc_set_buswidth(host, ios->bus_width);
1911 msdc_init_hw(host);
1915 dev_err(host->dev, "Failed to set vmmc power!\n");
1921 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1924 dev_err(host->dev, "Failed to set vqmmc power!\n");
1926 host->vqmmc_enabled = true;
1933 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1935 host->vqmmc_enabled = false;
1942 if (host->mclk != ios->clock || host->timing != ios->timing)
1943 msdc_set_mclk(host, ios->timing, ios->clock);
1963 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
1971 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
1992 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2001 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2003 u32 tune_reg = host->dev_comp->pad_tune_reg;
2005 if (host->top_base) {
2007 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);
2008 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);
2010 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2012 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,
2017 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2018 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2021 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2023 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2029 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2031 u32 tune_reg = host->dev_comp->pad_tune_reg;
2033 if (host->top_base) {
2035 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2037 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2040 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2042 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2047 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2048 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2051 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2053 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2061 struct msdc_host *host = mmc_priv(mmc);
2067 u32 tune_reg = host->dev_comp->pad_tune_reg;
2073 sdr_set_field(host->base + tune_reg,
2075 host->hs200_cmd_int_delay);
2077 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2078 for (i = 0; i < host->tuning_step; i++) {
2079 msdc_set_cmd_delay(host, i);
2095 final_rise_delay = get_best_delay(host, rise_delay);
2101 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2102 for (i = 0; i < host->tuning_step; i++) {
2103 msdc_set_cmd_delay(host, i);
2119 final_fall_delay = get_best_delay(host, fall_delay);
2126 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2129 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2132 msdc_set_cmd_delay(host, final_delay);
2134 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2137 for (i = 0; i < host->tuning_step; i++) {
2138 sdr_set_field(host->base + tune_reg,
2144 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2145 internal_delay_phase = get_best_delay(host, internal_delay);
2146 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2149 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2155 struct msdc_host *host = mmc_priv(mmc);
2163 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2164 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2168 sdr_set_field(host->base + MSDC_PAD_TUNE,
2170 host->hs200_cmd_int_delay);
2172 if (host->hs400_cmd_resp_sel_rising)
2173 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2175 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2178 sdr_set_field(host->base + PAD_CMD_TUNE,
2195 final_cmd_delay = get_best_delay(host, cmd_delay);
2196 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2200 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2206 struct msdc_host *host = mmc_priv(mmc);
2212 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2213 host->latch_ck);
2214 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2215 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2216 for (i = 0; i < host->tuning_step; i++) {
2217 msdc_set_data_delay(host, i);
2222 final_rise_delay = get_best_delay(host, rise_delay);
2228 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2229 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2230 for (i = 0; i < host->tuning_step; i++) {
2231 msdc_set_data_delay(host, i);
2236 final_fall_delay = get_best_delay(host, fall_delay);
2241 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2242 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2245 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2246 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2249 msdc_set_data_delay(host, final_delay);
2251 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2261 struct msdc_host *host = mmc_priv(mmc);
2267 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2268 host->latch_ck);
2270 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2271 sdr_clr_bits(host->base + MSDC_IOCON,
2273 for (i = 0; i < host->tuning_step; i++) {
2274 msdc_set_cmd_delay(host, i);
2275 msdc_set_data_delay(host, i);
2280 final_rise_delay = get_best_delay(host, rise_delay);
2286 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2287 sdr_set_bits(host->base + MSDC_IOCON,
2289 for (i = 0; i < host->tuning_step; i++) {
2290 msdc_set_cmd_delay(host, i);
2291 msdc_set_data_delay(host, i);
2296 final_fall_delay = get_best_delay(host, fall_delay);
2301 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2302 sdr_clr_bits(host->base + MSDC_IOCON,
2306 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2307 sdr_set_bits(host->base + MSDC_IOCON,
2312 msdc_set_cmd_delay(host, final_delay);
2313 msdc_set_data_delay(host, final_delay);
2315 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2321 struct msdc_host *host = mmc_priv(mmc);
2323 u32 tune_reg = host->dev_comp->pad_tune_reg;
2325 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2327 if (host->hs400_mode) {
2328 sdr_clr_bits(host->base + MSDC_IOCON,
2330 msdc_set_data_delay(host, 0);
2334 if (host->hs400_mode &&
2335 host->dev_comp->hs400_tune)
2340 dev_err(host->dev, "Tune response fail!\n");
2343 if (host->hs400_mode == false) {
2346 dev_err(host->dev, "Tune data fail!\n");
2350 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2351 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2352 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2353 if (host->top_base) {
2354 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2356 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2364 struct msdc_host *host = mmc_priv(mmc);
2365 host->hs400_mode = true;
2367 if (host->top_base)
2368 writel(host->hs400_ds_delay,
2369 host->top_base + EMMC50_PAD_DS_TUNE);
2371 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2373 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2375 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2382 struct msdc_host *host = mmc_priv(mmc);
2388 if (host->top_base) {
2389 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2391 if (host->hs400_ds_dly3)
2392 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2393 PAD_DS_DLY3, host->hs400_ds_dly3);
2395 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2396 if (host->hs400_ds_dly3)
2397 sdr_set_field(host->base + PAD_DS_TUNE,
2398 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2401 host->hs400_tuning = true;
2403 if (host->top_base)
2404 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2407 sdr_set_field(host->base + PAD_DS_TUNE,
2415 host->hs400_tuning = false;
2417 dly1_delay = get_best_delay(host, result_dly1);
2419 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2422 if (host->top_base)
2423 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2426 sdr_set_field(host->base + PAD_DS_TUNE,
2429 if (host->top_base)
2430 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2432 val = readl(host->base + PAD_DS_TUNE);
2434 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2439 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2445 struct msdc_host *host = mmc_priv(mmc);
2447 sdr_set_bits(host->base + EMMC_IOCON, 1);
2449 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2455 struct msdc_host *host = mmc_priv(mmc);
2457 spin_lock_irqsave(&host->lock, flags);
2458 __msdc_enable_sdio_irq(host, 1);
2459 spin_unlock_irqrestore(&host->lock, flags);
2464 struct msdc_host *host = mmc_priv(mmc);
2470 if (!host->internal_cd)
2473 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2483 struct msdc_host *host = mmc_priv(mmc);
2487 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2488 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2489 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2491 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2492 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2493 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2495 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2496 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2497 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2499 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2500 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2501 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2505 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2507 struct mmc_host *mmc = mmc_from_priv(host);
2517 hclk_freq = (u64)clk_get_rate(host->h_clk);
2535 host->cq_ssc1_time = 0x40;
2541 host->cq_ssc1_time = value;
2546 struct msdc_host *host = mmc_priv(mmc);
2550 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2552 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2554 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2556 msdc_set_timeout(host, 1000000000ULL, 0);
2559 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2564 struct msdc_host *host = mmc_priv(mmc);
2568 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2570 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2572 val = readl(host->base + MSDC_INT);
2573 writel(val, host->base + MSDC_INT);
2576 sdr_set_field(host->base + MSDC_DMA_CTRL,
2578 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2581 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2584 msdc_reset_hw(host);
2634 struct msdc_host *host)
2636 struct mmc_host *mmc = mmc_from_priv(host);
2639 &host->latch_ck);
2642 &host->hs400_ds_delay);
2645 &host->hs400_ds_dly3);
2648 &host->hs200_cmd_int_delay);
2651 &host->hs400_cmd_int_delay);
2655 host->hs400_cmd_resp_sel_rising = true;
2657 host->hs400_cmd_resp_sel_rising = false;
2660 &host->tuning_step)) {
2662 host->tuning_step = PAD_DELAY_FULL;
2664 host->tuning_step = PAD_DELAY_HALF;
2669 host->cqhci = true;
2671 host->cqhci = false;
2675 struct msdc_host *host)
2679 host->src_clk = devm_clk_get(&pdev->dev, "source");
2680 if (IS_ERR(host->src_clk))
2681 return PTR_ERR(host->src_clk);
2683 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2684 if (IS_ERR(host->h_clk))
2685 return PTR_ERR(host->h_clk);
2687 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2688 if (IS_ERR(host->bus_clk))
2689 host->bus_clk = NULL;
2692 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2693 if (IS_ERR(host->src_clk_cg))
2694 return PTR_ERR(host->src_clk_cg);
2703 if (!host->src_clk_cg) {
2704 host->src_clk_cg = clk_get_parent(host->src_clk);
2705 if (IS_ERR(host->src_clk_cg))
2706 return PTR_ERR(host->src_clk_cg);
2710 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2711 if (IS_ERR(host->sys_clk_cg))
2712 host->sys_clk_cg = NULL;
2714 host->bulk_clks[0].id = "pclk_cg";
2715 host->bulk_clks[1].id = "axi_cg";
2716 host->bulk_clks[2].id = "ahb_cg";
2718 host->bulk_clks);
2730 struct msdc_host *host;
2739 /* Allocate MMC host for this device */
2744 host = mmc_priv(mmc);
2749 host->base = devm_platform_ioremap_resource(pdev, 0);
2750 if (IS_ERR(host->base)) {
2751 ret = PTR_ERR(host->base);
2757 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2758 if (IS_ERR(host->top_base))
2759 host->top_base = NULL;
2766 ret = msdc_of_clock_parse(pdev, host);
2770 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2772 if (IS_ERR(host->reset)) {
2773 ret = PTR_ERR(host->reset);
2779 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2780 if (IS_ERR(host->crypto_clk))
2781 host->crypto_clk = NULL;
2786 host->irq = platform_get_irq(pdev, 0);
2787 if (host->irq < 0) {
2788 ret = host->irq;
2792 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2793 if (IS_ERR(host->pinctrl)) {
2794 ret = PTR_ERR(host->pinctrl);
2799 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2800 if (IS_ERR(host->pins_default)) {
2801 ret = PTR_ERR(host->pins_default);
2806 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2807 if (IS_ERR(host->pins_uhs)) {
2808 ret = PTR_ERR(host->pins_uhs);
2815 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2816 if (host->eint_irq > 0) {
2817 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2818 if (IS_ERR(host->pins_eint)) {
2820 host->pins_eint = NULL;
2827 msdc_of_property_parse(pdev, host);
2829 host->dev = &pdev->dev;
2830 host->dev_comp = of_device_get_match_data(&pdev->dev);
2831 host->src_clk_freq = clk_get_rate(host->src_clk);
2832 /* Set host parameters to mmc */
2834 if (host->dev_comp->clk_div_bits == 8)
2835 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2837 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2841 host->dev_comp->use_internal_cd) {
2846 host->internal_cd = true;
2853 if (host->cqhci)
2857 if (host->dev_comp->support_64g)
2864 if (host->dev_comp->support_64g)
2865 host->dma_mask = DMA_BIT_MASK(36);
2867 host->dma_mask = DMA_BIT_MASK(32);
2868 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2870 host->timeout_clks = 3 * 1048576;
2871 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2873 &host->dma.gpd_addr, GFP_KERNEL);
2874 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2876 &host->dma.bd_addr, GFP_KERNEL);
2877 if (!host->dma.gpd || !host->dma.bd) {
2881 msdc_init_gpd_bd(host, &host->dma);
2882 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2883 spin_lock_init(&host->lock);
2886 ret = msdc_ungate_clock(host);
2891 msdc_init_hw(host);
2894 host->cq_host = devm_kzalloc(mmc->parent,
2895 sizeof(*host->cq_host),
2897 if (!host->cq_host) {
2901 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2902 host->cq_host->mmio = host->base + 0x800;
2903 host->cq_host->ops = &msdc_cmdq_ops;
2904 ret = cqhci_init(host->cq_host, mmc, true);
2912 msdc_cqe_cit_cal(host, 2350);
2915 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2916 IRQF_TRIGGER_NONE, pdev->name, host);
2920 pm_runtime_set_active(host->dev);
2921 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2922 pm_runtime_use_autosuspend(host->dev);
2923 pm_runtime_enable(host->dev);
2931 pm_runtime_disable(host->dev);
2934 msdc_deinit_hw(host);
2935 msdc_gate_clock(host);
2937 if (host->dma.gpd)
2940 host->dma.gpd, host->dma.gpd_addr);
2941 if (host->dma.bd)
2944 host->dma.bd, host->dma.bd_addr);
2954 struct msdc_host *host;
2957 host = mmc_priv(mmc);
2959 pm_runtime_get_sync(host->dev);
2963 msdc_deinit_hw(host);
2964 msdc_gate_clock(host);
2966 pm_runtime_disable(host->dev);
2967 pm_runtime_put_noidle(host->dev);
2970 host->dma.gpd, host->dma.gpd_addr);
2972 host->dma.bd, host->dma.bd_addr);
2977 static void msdc_save_reg(struct msdc_host *host)
2979 u32 tune_reg = host->dev_comp->pad_tune_reg;
2981 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2982 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2983 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2984 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2985 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2986 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2987 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2988 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2989 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2990 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2991 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2992 if (host->top_base) {
2993 host->save_para.emmc_top_control =
2994 readl(host->top_base + EMMC_TOP_CONTROL);
2995 host->save_para.emmc_top_cmd =
2996 readl(host->top_base + EMMC_TOP_CMD);
2997 host->save_para.emmc50_pad_ds_tune =
2998 readl(host->top_base + EMMC50_PAD_DS_TUNE);
3000 host->save_para.pad_tune = readl(host->base + tune_reg);
3004 static void msdc_restore_reg(struct msdc_host *host)
3006 struct mmc_host *mmc = mmc_from_priv(host);
3007 u32 tune_reg = host->dev_comp->pad_tune_reg;
3009 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3010 writel(host->save_para.iocon, host->base + MSDC_IOCON);
3011 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3012 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3013 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3014 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3015 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3016 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3017 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3018 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3019 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3020 if (host->top_base) {
3021 writel(host->save_para.emmc_top_control,
3022 host->top_base + EMMC_TOP_CONTROL);
3023 writel(host->save_para.emmc_top_cmd,
3024 host->top_base + EMMC_TOP_CMD);
3025 writel(host->save_para.emmc50_pad_ds_tune,
3026 host->top_base + EMMC50_PAD_DS_TUNE);
3028 writel(host->save_para.pad_tune, host->base + tune_reg);
3032 __msdc_enable_sdio_irq(host, 1);
3038 struct msdc_host *host = mmc_priv(mmc);
3040 msdc_save_reg(host);
3043 if (host->pins_eint) {
3044 disable_irq(host->irq);
3045 pinctrl_select_state(host->pinctrl, host->pins_eint);
3048 __msdc_enable_sdio_irq(host, 0);
3050 msdc_gate_clock(host);
3057 struct msdc_host *host = mmc_priv(mmc);
3060 ret = msdc_ungate_clock(host);
3064 msdc_restore_reg(host);
3066 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3067 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3068 enable_irq(host->irq);
3076 struct msdc_host *host = mmc_priv(mmc);
3084 val = readl(host->base + MSDC_INT);
3085 writel(val, host->base + MSDC_INT);
3092 if (sdio_irq_claimed(mmc) && host->pins_eint)
3101 struct msdc_host *host = mmc_priv(mmc);
3103 if (sdio_irq_claimed(mmc) && host->pins_eint)