Lines Matching refs:host
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
23 #include <linux/mmc/host.h>
49 static void mmci_variant_init(struct mmci_host *host);
50 static void ux500_variant_init(struct mmci_host *host);
51 static void ux500v2_variant_init(struct mmci_host *host);
373 struct mmci_host *host = mmc_priv(mmc);
377 spin_lock_irqsave(&host->lock, flags);
378 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
380 spin_unlock_irqrestore(&host->lock, flags);
385 static void mmci_reg_delay(struct mmci_host *host)
394 if (host->cclk < 25000000)
401 * This must be called with host->lock held
403 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
405 if (host->clk_reg != clk) {
406 host->clk_reg = clk;
407 writel(clk, host->base + MMCICLOCK);
412 * This must be called with host->lock held
414 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
416 if (host->pwr_reg != pwr) {
417 host->pwr_reg = pwr;
418 writel(pwr, host->base + MMCIPOWER);
423 * This must be called with host->lock held
425 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
428 datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag |
429 host->variant->datactrl_mask_sdio);
431 if (host->datactrl_reg != datactrl) {
432 host->datactrl_reg = datactrl;
433 writel(datactrl, host->base + MMCIDATACTRL);
438 * This must be called with host->lock held
440 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
442 struct variant_data *variant = host->variant;
446 host->cclk = 0;
450 host->cclk = host->mclk;
451 } else if (desired >= host->mclk) {
455 host->cclk = host->mclk;
463 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
466 host->cclk = host->mclk / (clk + 2);
472 clk = host->mclk / (2 * desired) - 1;
475 host->cclk = host->mclk / (2 * (clk + 1));
485 host->mmc->actual_clock = host->cclk;
487 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
489 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
492 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
493 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
496 mmci_write_clkreg(host, clk);
499 static void mmci_dma_release(struct mmci_host *host)
501 if (host->ops && host->ops->dma_release)
502 host->ops->dma_release(host);
504 host->use_dma = false;
507 static void mmci_dma_setup(struct mmci_host *host)
509 if (!host->ops || !host->ops->dma_setup)
512 if (host->ops->dma_setup(host))
516 host->next_cookie = 1;
518 host->use_dma = true;
524 static int mmci_validate_data(struct mmci_host *host,
527 struct variant_data *variant = host->variant;
532 dev_err(mmc_dev(host->mmc),
537 if (host->ops && host->ops->validate_data)
538 return host->ops->validate_data(host, data);
543 static int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
547 if (!host->ops || !host->ops->prep_data)
550 err = host->ops->prep_data(host, data, next);
553 data->host_cookie = ++host->next_cookie < 0 ?
554 1 : host->next_cookie;
559 static void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
562 if (host->ops && host->ops->unprep_data)
563 host->ops->unprep_data(host, data, err);
568 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
570 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
572 if (host->ops && host->ops->get_next_data)
573 host->ops->get_next_data(host, data);
576 static int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
578 struct mmc_data *data = host->data;
581 if (!host->use_dma)
584 ret = mmci_prep_data(host, data, false);
588 if (!host->ops || !host->ops->dma_start)
592 dev_vdbg(mmc_dev(host->mmc),
596 ret = host->ops->dma_start(host, &datactrl);
601 mmci_write_datactrlreg(host, datactrl);
608 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
609 host->base + MMCIMASK0);
613 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
615 if (!host->use_dma)
618 if (host->ops && host->ops->dma_finalize)
619 host->ops->dma_finalize(host, data);
622 static void mmci_dma_error(struct mmci_host *host)
624 if (!host->use_dma)
627 if (host->ops && host->ops->dma_error)
628 host->ops->dma_error(host);
632 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
634 writel(0, host->base + MMCICOMMAND);
636 BUG_ON(host->data);
638 host->mrq = NULL;
639 host->cmd = NULL;
641 mmc_request_done(host->mmc, mrq);
644 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
646 void __iomem *base = host->base;
647 struct variant_data *variant = host->variant;
649 if (host->singleirq) {
661 host->mask1_reg = mask;
664 static void mmci_stop_data(struct mmci_host *host)
666 mmci_write_datactrlreg(host, 0);
667 mmci_set_mask1(host, 0);
668 host->data = NULL;
671 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
680 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
683 static u32 mmci_get_dctrl_cfg(struct mmci_host *host)
685 return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host);
688 static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host)
690 return MCI_DPSM_ENABLE | (host->data->blksz << 16);
693 static void ux500_busy_clear_mask_done(struct mmci_host *host)
695 void __iomem *base = host->base;
697 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
699 ~host->variant->busy_detect_mask, base + MMCIMASK0);
700 host->busy_state = MMCI_BUSY_DONE;
701 host->busy_status = 0;
707 * host->busy_status until we know the card is not busy any more.
721 static bool ux500_busy_complete(struct mmci_host *host, struct mmc_command *cmd,
724 void __iomem *base = host->base;
729 ux500_busy_clear_mask_done(host);
737 switch (host->busy_state) {
743 * store the status in host->busy_status.
754 * host->busy_status, which is what it should be in IDLE.
756 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND);
760 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
761 if (status & host->variant->busy_detect_flag) {
763 host->variant->busy_detect_mask,
765 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ;
766 schedule_delayed_work(&host->ux500_busy_timeout_work,
772 dev_dbg(mmc_dev(host->mmc),
774 ux500_busy_clear_mask_done(host);
789 if (status & host->variant->busy_detect_flag) {
790 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
791 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
792 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ;
794 dev_dbg(mmc_dev(host->mmc),
797 cancel_delayed_work(&host->ux500_busy_timeout_work);
798 ux500_busy_clear_mask_done(host);
803 if (!(status & host->variant->busy_detect_flag)) {
804 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
805 writel(host->variant->busy_detect_mask, base + MMCICLEAR);
806 cancel_delayed_work(&host->ux500_busy_timeout_work);
807 ux500_busy_clear_mask_done(host);
809 dev_dbg(mmc_dev(host->mmc),
816 dev_dbg(mmc_dev(host->mmc), "fell through on state %d, CMD%02x\n",
817 host->busy_state, cmd->opcode);
822 return (host->busy_state == MMCI_BUSY_DONE);
844 int mmci_dmae_setup(struct mmci_host *host)
849 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
853 host->dma_priv = dmae;
855 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx");
862 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx");
865 dev_warn(mmc_dev(host->mmc),
888 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
899 if (max_seg_size < host->mmc->max_seg_size)
900 host->mmc->max_seg_size = max_seg_size;
906 if (max_seg_size < host->mmc->max_seg_size)
907 host->mmc->max_seg_size = max_seg_size;
911 mmci_dmae_release(host);
922 void mmci_dmae_release(struct mmci_host *host)
924 struct mmci_dmae_priv *dmae = host->dma_priv;
933 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
935 struct mmci_dmae_priv *dmae = host->dma_priv;
947 void mmci_dmae_error(struct mmci_host *host)
949 struct mmci_dmae_priv *dmae = host->dma_priv;
951 if (!dma_inprogress(host))
954 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
956 host->dma_in_progress = false;
959 host->data->host_cookie = 0;
961 mmci_dma_unmap(host, host->data);
964 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
966 struct mmci_dmae_priv *dmae = host->dma_priv;
970 if (!dma_inprogress(host))
975 status = readl(host->base + MMCISTATUS);
988 mmci_dma_error(host);
992 mmci_dma_unmap(host, data);
1000 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
1001 mmci_dma_release(host);
1004 host->dma_in_progress = false;
1010 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
1014 struct mmci_dmae_priv *dmae = host->dma_priv;
1015 struct variant_data *variant = host->variant;
1017 .src_addr = host->phybase + MMCIFIFO,
1018 .dst_addr = host->phybase + MMCIFIFO,
1056 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz))
1065 if (host->variant->qcom_dml)
1085 int mmci_dmae_prep_data(struct mmci_host *host,
1089 struct mmci_dmae_priv *dmae = host->dma_priv;
1092 if (!host->use_dma)
1096 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
1102 return _mmci_dmae_prep_data(host, data, &dmae->cur,
1106 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
1108 struct mmci_dmae_priv *dmae = host->dma_priv;
1111 host->dma_in_progress = true;
1114 host->dma_in_progress = false;
1124 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
1126 struct mmci_dmae_priv *dmae = host->dma_priv;
1129 if (!host->use_dma)
1140 void mmci_dmae_unprep_data(struct mmci_host *host,
1144 struct mmci_dmae_priv *dmae = host->dma_priv;
1146 if (!host->use_dma)
1149 mmci_dma_unmap(host, data);
1164 host->dma_in_progress = false;
1190 static void mmci_variant_init(struct mmci_host *host)
1192 host->ops = &mmci_variant_ops;
1195 static void ux500_variant_init(struct mmci_host *host)
1197 host->ops = &mmci_variant_ops;
1198 host->ops->busy_complete = ux500_busy_complete;
1201 static void ux500v2_variant_init(struct mmci_host *host)
1203 host->ops = &mmci_variant_ops;
1204 host->ops->busy_complete = ux500_busy_complete;
1205 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg;
1210 struct mmci_host *host = mmc_priv(mmc);
1218 if (mmci_validate_data(host, data))
1221 mmci_prep_data(host, data, true);
1227 struct mmci_host *host = mmc_priv(mmc);
1233 mmci_unprep_data(host, data, err);
1236 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
1238 struct variant_data *variant = host->variant;
1243 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1246 host->data = data;
1247 host->size = data->blksz * data->blocks;
1250 clks = (unsigned long long)data->timeout_ns * host->cclk;
1255 base = host->base;
1257 writel(host->size, base + MMCIDATALENGTH);
1259 datactrl = host->ops->get_datactrl_cfg(host);
1260 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0;
1262 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1274 (host->size < 8 ||
1275 (host->size <= 8 && host->mclk > 50000000)))
1276 clk = host->clk_reg & ~variant->clkreg_enable;
1278 clk = host->clk_reg | variant->clkreg_enable;
1280 mmci_write_clkreg(host, clk);
1283 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1284 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1291 if (!mmci_dma_start(host, datactrl))
1295 mmci_init_sg(host, data);
1305 if (host->size < variant->fifohalfsize)
1315 mmci_write_datactrlreg(host, datactrl);
1317 mmci_set_mask1(host, irqmask);
1321 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1323 void __iomem *base = host->base;
1327 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1330 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1332 mmci_reg_delay(host);
1335 if (host->variant->cmdreg_stop &&
1337 c |= host->variant->cmdreg_stop;
1339 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1342 c |= host->variant->cmdreg_lrsp_crc;
1344 c |= host->variant->cmdreg_srsp_crc;
1346 c |= host->variant->cmdreg_srsp;
1349 host->busy_status = 0;
1350 host->busy_state = MMCI_BUSY_DONE;
1356 if (busy_resp && host->variant->busy_timeout) {
1357 if (cmd->busy_timeout > host->mmc->max_busy_timeout)
1358 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk;
1360 clks = (unsigned long long)cmd->busy_timeout * host->cclk;
1363 writel_relaxed(clks, host->base + MMCIDATATIMER);
1366 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE)
1367 host->ops->pre_sig_volt_switch(host);
1373 c |= host->variant->data_cmd_enable;
1375 host->cmd = cmd;
1381 static void mmci_stop_command(struct mmci_host *host)
1383 host->stop_abort.error = 0;
1384 mmci_start_command(host, &host->stop_abort, 0);
1388 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1398 status_err = status & (host->variant->start_err |
1406 mmci_dma_error(host);
1411 * on the MMC bus, not on the host side. On reads, this
1415 if (!host->variant->datacnt_useless) {
1416 remain = readl(host->base + MMCIDATACNT);
1422 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1435 if (success > host->variant->fifosize)
1436 success -= host->variant->fifosize;
1445 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1448 mmci_dma_finalize(host, data);
1450 mmci_stop_data(host);
1457 if (host->variant->cmdreg_stop && data->error)
1458 mmci_stop_command(host);
1460 mmci_request_end(host, data->mrq);
1461 } else if (host->mrq->sbc && !data->error) {
1462 mmci_request_end(host, data->mrq);
1464 mmci_start_command(host, data->stop, 0);
1470 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1474 void __iomem *base = host->base;
1480 sbc = (cmd == host->mrq->sbc);
1488 if (host->variant->busy_timeout && busy_resp)
1491 if (!((status | host->busy_status) &
1496 if (busy_resp && host->variant->busy_detect)
1497 if (!host->ops->busy_complete(host, cmd, status, err_msk))
1500 host->cmd = NULL;
1506 } else if (host->variant->busy_timeout && busy_resp &&
1513 host->irq_action = IRQ_WAKE_THREAD;
1522 if (host->data) {
1524 mmci_dma_error(host);
1526 mmci_stop_data(host);
1527 if (host->variant->cmdreg_stop && cmd->error) {
1528 mmci_stop_command(host);
1533 if (host->irq_action != IRQ_WAKE_THREAD)
1534 mmci_request_end(host, host->mrq);
1537 mmci_start_command(host, host->mrq->cmd, 0);
1538 } else if (!host->variant->datactrl_first &&
1540 mmci_start_data(host, cmd->data);
1544 static char *ux500_state_str(struct mmci_host *host)
1546 switch (host->busy_state) {
1565 struct mmci_host *host = container_of(work, struct mmci_host,
1570 spin_lock_irqsave(&host->lock, flags);
1572 if (host->cmd) {
1574 status = readl(host->base + MMCISTATUS);
1575 if (status & host->variant->busy_detect_flag) {
1577 dev_err(mmc_dev(host->mmc),
1579 ux500_state_str(host), host->cmd->opcode);
1581 dev_err(mmc_dev(host->mmc),
1583 ux500_state_str(host), host->cmd->opcode);
1586 mmci_cmd_irq(host, host->cmd, status);
1589 spin_unlock_irqrestore(&host->lock, flags);
1592 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1594 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1597 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1604 return host->variant->fifohalfsize;
1611 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1613 void __iomem *base = host->base;
1615 u32 status = readl(host->base + MMCISTATUS);
1616 int host_remain = host->size;
1619 int count = host->get_rx_fifocnt(host, status, host_remain);
1659 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1661 struct variant_data *variant = host->variant;
1662 void __iomem *base = host->base;
1699 struct mmci_host *host = dev_id;
1700 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1701 struct variant_data *variant = host->variant;
1702 void __iomem *base = host->base;
1707 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1731 len = mmci_pio_read(host, buffer, remain);
1733 len = mmci_pio_write(host, buffer, remain, status);
1737 host->size -= len;
1752 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1753 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1761 if (host->size == 0) {
1762 mmci_set_mask1(host, 0);
1769 static void mmci_write_sdio_irq_bit(struct mmci_host *host, int enable)
1771 void __iomem *base = host->base;
1780 static void mmci_signal_sdio_irq(struct mmci_host *host, u32 status)
1783 mmci_write_sdio_irq_bit(host, 0);
1784 sdio_signal_irq(host->mmc);
1793 struct mmci_host *host = dev_id;
1796 spin_lock(&host->lock);
1797 host->irq_action = IRQ_HANDLED;
1800 status = readl(host->base + MMCISTATUS);
1804 if (host->singleirq) {
1805 if (status & host->mask1_reg)
1808 status &= ~host->variant->irq_pio_mask;
1815 status &= readl(host->base + MMCIMASK0);
1816 if (host->variant->busy_detect)
1817 writel(status & ~host->variant->busy_detect_mask,
1818 host->base + MMCICLEAR);
1820 writel(status, host->base + MMCICLEAR);
1822 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1824 if (host->variant->reversed_irq_handling) {
1825 mmci_data_irq(host, host->data, status);
1826 mmci_cmd_irq(host, host->cmd, status);
1828 mmci_cmd_irq(host, host->cmd, status);
1829 mmci_data_irq(host, host->data, status);
1832 if (host->variant->supports_sdio_irq)
1833 mmci_signal_sdio_irq(host, status);
1839 if (host->variant->busy_detect_flag)
1840 status &= ~host->variant->busy_detect_flag;
1844 spin_unlock(&host->lock);
1846 return host->irq_action;
1857 struct mmci_host *host = dev_id;
1860 if (host->rst) {
1861 reset_control_assert(host->rst);
1863 reset_control_deassert(host->rst);
1866 spin_lock_irqsave(&host->lock, flags);
1867 writel(host->clk_reg, host->base + MMCICLOCK);
1868 writel(host->pwr_reg, host->base + MMCIPOWER);
1869 writel(MCI_IRQENABLE | host->variant->start_err,
1870 host->base + MMCIMASK0);
1872 host->irq_action = IRQ_HANDLED;
1873 mmci_request_end(host, host->mrq);
1874 spin_unlock_irqrestore(&host->lock, flags);
1876 return host->irq_action;
1881 struct mmci_host *host = mmc_priv(mmc);
1884 WARN_ON(host->mrq != NULL);
1886 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1892 spin_lock_irqsave(&host->lock, flags);
1894 host->mrq = mrq;
1897 mmci_get_next_data(host, mrq->data);
1900 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1901 mmci_start_data(host, mrq->data);
1904 mmci_start_command(host, mrq->sbc, 0);
1906 mmci_start_command(host, mrq->cmd, 0);
1908 spin_unlock_irqrestore(&host->lock, flags);
1913 struct mmci_host *host = mmc_priv(mmc);
1916 if (!host->variant->busy_detect)
1919 if (host->variant->busy_timeout && mmc->actual_clock)
1928 struct mmci_host *host = mmc_priv(mmc);
1929 struct variant_data *variant = host->variant;
1939 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1941 host->vqmmc_enabled = false;
1958 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1964 host->vqmmc_enabled = true;
1977 pwr |= host->pwr_reg_add;
1996 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
2008 if (host->variant->explicit_mclk_control &&
2009 ios->clock != host->clock_cache) {
2010 ret = clk_set_rate(host->clk, ios->clock);
2012 dev_err(mmc_dev(host->mmc),
2015 host->mclk = clk_get_rate(host->clk);
2017 host->clock_cache = ios->clock;
2019 spin_lock_irqsave(&host->lock, flags);
2021 if (host->ops && host->ops->set_clkreg)
2022 host->ops->set_clkreg(host, ios->clock);
2024 mmci_set_clkreg(host, ios->clock);
2028 if (host->ops && host->ops->set_pwrreg)
2029 host->ops->set_pwrreg(host, pwr);
2031 mmci_write_pwrreg(host, pwr);
2033 mmci_reg_delay(host);
2035 spin_unlock_irqrestore(&host->lock, flags);
2040 struct mmci_host *host = mmc_priv(mmc);
2041 struct mmci_platform_data *plat = host->plat;
2048 status = plat->status(mmc_dev(host->mmc));
2055 struct mmci_host *host = mmc_priv(mmc);
2060 if (!ret && host->ops && host->ops->post_sig_volt_switch)
2061 ret = host->ops->post_sig_volt_switch(host, ios);
2073 struct mmci_host *host = mmc_priv(mmc);
2080 spin_lock_irqsave(&host->lock, flags);
2081 mmci_write_sdio_irq_bit(host, enable);
2082 spin_unlock_irqrestore(&host->lock, flags);
2092 struct mmci_host *host = mmc_priv(mmc);
2095 spin_lock_irqsave(&host->lock, flags);
2096 mmci_write_sdio_irq_bit(host, 1);
2097 spin_unlock_irqrestore(&host->lock, flags);
2113 struct mmci_host *host = mmc_priv(mmc);
2123 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
2154 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN;
2171 struct mmci_host *host = mmc_priv(mmc);
2178 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
2180 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
2182 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
2184 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
2186 host->pwr_reg_add |= MCI_ST_CMDDIREN;
2188 host->pwr_reg_add |= MCI_ST_FBCLKEN;
2190 host->pwr_reg_add |= MCI_STM32_DIRPOL;
2192 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
2210 struct mmci_host *host;
2230 host = mmc_priv(mmc);
2231 host->mmc = mmc;
2232 host->mmc_ops = &mmci_ops;
2244 host->pinctrl = devm_pinctrl_get(&dev->dev);
2245 if (IS_ERR(host->pinctrl)) {
2247 ret = PTR_ERR(host->pinctrl);
2251 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
2253 if (IS_ERR(host->pins_opendrain)) {
2255 ret = PTR_ERR(host->pins_opendrain);
2260 host->hw_designer = amba_manf(dev);
2261 host->hw_revision = amba_rev(dev);
2262 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
2263 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
2265 host->clk = devm_clk_get(&dev->dev, NULL);
2266 if (IS_ERR(host->clk)) {
2267 ret = PTR_ERR(host->clk);
2271 ret = clk_prepare_enable(host->clk);
2276 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
2278 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
2280 host->plat = plat;
2281 host->variant = variant;
2282 host->mclk = clk_get_rate(host->clk);
2288 if (host->mclk > variant->f_max) {
2289 ret = clk_set_rate(host->clk, variant->f_max);
2292 host->mclk = clk_get_rate(host->clk);
2294 host->mclk);
2297 host->phybase = dev->res.start;
2298 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
2299 if (IS_ERR(host->base)) {
2300 ret = PTR_ERR(host->base);
2305 variant->init(host);
2314 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
2316 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
2318 mmc->f_min = clk_round_rate(host->clk, 100000);
2320 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
2330 min(host->mclk, mmc->f_max);
2333 fmax : min(host->mclk, fmax);
2338 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
2339 if (IS_ERR(host->rst)) {
2340 ret = PTR_ERR(host->rst);
2343 ret = reset_control_deassert(host->rst);
2370 mmci_write_datactrlreg(host,
2371 host->variant->busy_dpsm_flag);
2375 if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) {
2381 mmci_write_datactrlreg(host,
2382 host->variant->datactrl_mask_sdio);
2390 host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
2391 host->stop_abort.arg = 0;
2392 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
2426 spin_lock_init(&host->lock);
2428 writel(0, host->base + MMCIMASK0);
2431 writel(0, host->base + MMCIMASK1);
2433 writel(0xfff, host->base + MMCICLEAR);
2454 DRIVER_NAME " (cmd)", host);
2459 host->singleirq = true;
2462 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2467 if (host->variant->busy_detect)
2468 INIT_DELAYED_WORK(&host->ux500_busy_timeout_work,
2471 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2480 mmci_dma_setup(host);
2493 clk_disable_unprepare(host->clk);
2504 struct mmci_host *host = mmc_priv(mmc);
2505 struct variant_data *variant = host->variant;
2515 writel(0, host->base + MMCIMASK0);
2518 writel(0, host->base + MMCIMASK1);
2520 writel(0, host->base + MMCICOMMAND);
2521 writel(0, host->base + MMCIDATACTRL);
2523 mmci_dma_release(host);
2524 clk_disable_unprepare(host->clk);
2530 static void mmci_save(struct mmci_host *host)
2534 spin_lock_irqsave(&host->lock, flags);
2536 writel(0, host->base + MMCIMASK0);
2537 if (host->variant->pwrreg_nopower) {
2538 writel(0, host->base + MMCIDATACTRL);
2539 writel(0, host->base + MMCIPOWER);
2540 writel(0, host->base + MMCICLOCK);
2542 mmci_reg_delay(host);
2544 spin_unlock_irqrestore(&host->lock, flags);
2547 static void mmci_restore(struct mmci_host *host)
2551 spin_lock_irqsave(&host->lock, flags);
2553 if (host->variant->pwrreg_nopower) {
2554 writel(host->clk_reg, host->base + MMCICLOCK);
2555 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2556 writel(host->pwr_reg, host->base + MMCIPOWER);
2558 writel(MCI_IRQENABLE | host->variant->start_err,
2559 host->base + MMCIMASK0);
2560 mmci_reg_delay(host);
2562 spin_unlock_irqrestore(&host->lock, flags);
2571 struct mmci_host *host = mmc_priv(mmc);
2573 mmci_save(host);
2574 clk_disable_unprepare(host->clk);
2586 struct mmci_host *host = mmc_priv(mmc);
2587 clk_prepare_enable(host->clk);
2588 mmci_restore(host);