Lines Matching refs:clock
106 ret = clk_set_rate(host->ciu_clk, ios->clock);
108 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
191 unsigned int clock;
193 clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
195 ret = clk_set_rate(host->biu_clk, clock);
197 dev_warn(host->dev, "failed to set rate %uHz\n", clock);
304 if (!ios->clock || ios->clock == priv->cur_speed)
307 wanted = ios->clock * (GENCLK_DIV + 1);
340 * A clock cycle is divided into 32 phases,