Lines Matching refs:intr_cause
362 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
461 bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
469 !!(hw->intr_cause & TXE_INTR_IN_READY),
470 !!(hw->intr_cause & TXE_INTR_READINESS),
471 !!(hw->intr_cause & TXE_INTR_ALIVENESS),
472 !!(hw->intr_cause & TXE_INTR_OUT_DB));
936 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
999 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
1001 hw->intr_cause |= TXE_INTR_IN_READY;
1075 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1101 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1115 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1129 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {