misc/mchp_pci1xxxx/mchp_pci1xxxx_gpio.c

3 // pci1xxxx gpio driver
7 #include <linux/gpio/driver.h>
40 	struct gpio_chip gpio;
45 static int pci1xxxx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
47 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
76 static int pci1xxxx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
78 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
89 static int pci1xxxx_gpio_get(struct gpio_chip *gpio, unsigned int nr)
91 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
96 static int pci1xxxx_gpio_direction_output(struct gpio_chip *gpio,
99 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
117 static void pci1xxxx_gpio_set(struct gpio_chip *gpio,
120 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
128 static int pci1xxxx_gpio_set_config(struct gpio_chip *gpio, unsigned int offset,
131 	struct pci1xxxx_gpio *priv = gpiochip_get_data(gpio);
163 	unsigned int gpio = irqd_to_hwirq(data);
167 	pci1xxx_assign_bit(priv->reg_base, INTR_STAT_OFFSET(gpio), (gpio % 32), true);
175 	unsigned int gpio = irqd_to_hwirq(data);
179 		gpiochip_enable_irq(chip, gpio);
181 	pci1xxx_assign_bit(priv->reg_base, INTR_MASK_OFFSET(gpio), (gpio % 32), set);
184 		gpiochip_disable_irq(chip, gpio);
201 	unsigned int gpio = irqd_to_hwirq(data);
202 	unsigned int bitpos = gpio % 32;
205 		pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
207 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio),
211 		pci1xxx_assign_bit(priv->reg_base, INTR_HI_TO_LO_EDGE_CONFIG(gpio),
216 		pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
218 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
222 		pci1xxx_assign_bit(priv->reg_base, INTR_LO_TO_HI_EDGE_CONFIG(gpio),
227 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
229 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
231 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
237 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_CONFIG_OFFSET(gpio),
239 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio),
241 		pci1xxx_assign_bit(priv->reg_base, MODE_OFFSET(gpio), bitpos,
247 		pci1xxx_assign_bit(priv->reg_base, INTR_LEVEL_MASK_OFFSET(gpio), bitpos, true);
255 	struct gpio_chip *gc =  &priv->gpio;
334 	struct gpio_chip *gchip = &priv->gpio;
359 	girq = &priv->gpio.irq;
410 	return devm_gpiochip_add_data(&aux_dev->dev, &priv->gpio, priv);