misc/eeprom/eeprom_93xx46.c

67 static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev)
69 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ;
72 static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev)
74 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH;
77 static inline bool has_quirk_extra_read_cycle(struct eeprom_93xx46_dev *edev)
79 	return edev->pdata->quirks & EEPROM_93XX46_QUIRK_EXTRA_READ_CYCLE;
85 	struct eeprom_93xx46_dev *edev = priv;
90 	if (unlikely(off >= edev->size))
92 	if ((off + count) > edev->size)
93 		count = edev->size - off;
97 	mutex_lock(&edev->lock);
99 	if (edev->pdata->prepare)
100 		edev->pdata->prepare(edev);
103 	bits = edev->addrlen + 3;
108 		u16 cmd_addr = OP_READ << edev->addrlen;
111 		if (edev->pdata->flags & EE_ADDR8) {
113 			if (has_quirk_single_word_read(edev))
117 			if (has_quirk_single_word_read(edev))
121 		dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n",
122 			cmd_addr, edev->spi->max_speed_hz);
124 		if (has_quirk_extra_read_cycle(edev)) {
141 		err = spi_sync(edev->spi, &m);
146 			dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n",
156 	if (edev->pdata->finish)
157 		edev->pdata->finish(edev);
159 	mutex_unlock(&edev->lock);
164 static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on)
172 	bits = edev->addrlen + 3;
174 	cmd_addr = OP_START << edev->addrlen;
175 	if (edev->pdata->flags & EE_ADDR8)
180 	if (has_quirk_instruction_length(edev)) {
185 	dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n",
196 	mutex_lock(&edev->lock);
198 	if (edev->pdata->prepare)
199 		edev->pdata->prepare(edev);
201 	ret = spi_sync(edev->spi, &m);
205 		dev_err(&edev->spi->dev, "erase/write %sable error %d\n",
208 	if (edev->pdata->finish)
209 		edev->pdata->finish(edev);
211 	mutex_unlock(&edev->lock);
216 eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev,
224 	if (unlikely(off >= edev->size))
228 	bits = edev->addrlen + 3;
230 	cmd_addr = OP_WRITE << edev->addrlen;
232 	if (edev->pdata->flags & EE_ADDR8) {
240 	dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr);
255 	ret = spi_sync(edev->spi, &m);
264 	struct eeprom_93xx46_dev *edev = priv;
268 	if (unlikely(off >= edev->size))
270 	if ((off + count) > edev->size)
271 		count = edev->size - off;
276 	if (edev->pdata->flags & EE_ADDR16) {
282 	ret = eeprom_93xx46_ew(edev, 1);
286 	mutex_lock(&edev->lock);
288 	if (edev->pdata->prepare)
289 		edev->pdata->prepare(edev);
292 		ret = eeprom_93xx46_write_word(edev, &buf[i], off + i);
294 			dev_err(&edev->spi->dev, "write failed at %d: %d\n",
300 	if (edev->pdata->finish)
301 		edev->pdata->finish(edev);
303 	mutex_unlock(&edev->lock);
306 	eeprom_93xx46_ew(edev, 0);
310 static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev)
312 	struct eeprom_93xx46_platform_data *pd = edev->pdata;
319 	bits = edev->addrlen + 3;
321 	cmd_addr = OP_START << edev->addrlen;
322 	if (edev->pdata->flags & EE_ADDR8)
327 	if (has_quirk_instruction_length(edev)) {
332 	dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits);
342 	mutex_lock(&edev->lock);
344 	if (edev->pdata->prepare)
345 		edev->pdata->prepare(edev);
347 	ret = spi_sync(edev->spi, &m);
349 		dev_err(&edev->spi->dev, "erase error %d\n", ret);
354 		pd->finish(edev);
356 	mutex_unlock(&edev->lock);
364 	struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev);
369 		ret = eeprom_93xx46_ew(edev, 1);
372 		ret = eeprom_93xx46_eral(edev);
375 		ret = eeprom_93xx46_ew(edev, 0);
385 	struct eeprom_93xx46_dev *edev = context;
387 	gpiod_set_value_cansleep(edev->pdata->select, 1);
392 	struct eeprom_93xx46_dev *edev = context;
394 	gpiod_set_value_cansleep(edev->pdata->select, 0);
480 	struct eeprom_93xx46_dev *edev;
495 	edev = devm_kzalloc(&spi->dev, sizeof(*edev), GFP_KERNEL);
496 	if (!edev)
500 		edev->size = 128;
502 		edev->size = 256;
504 		edev->size = 512;
511 		edev->addrlen = ilog2(edev->size);
513 		edev->addrlen = ilog2(edev->size) - 1;
519 	mutex_init(&edev->lock);
521 	edev->spi = spi;
522 	edev->pdata = pd;
524 	edev->nvmem_config.type = NVMEM_TYPE_EEPROM;
525 	edev->nvmem_config.name = dev_name(&spi->dev);
526 	edev->nvmem_config.dev = &spi->dev;
527 	edev->nvmem_config.read_only = pd->flags & EE_READONLY;
528 	edev->nvmem_config.root_only = true;
529 	edev->nvmem_config.owner = THIS_MODULE;
530 	edev->nvmem_config.compat = true;
531 	edev->nvmem_config.base_dev = &spi->dev;
532 	edev->nvmem_config.reg_read = eeprom_93xx46_read;
533 	edev->nvmem_config.reg_write = eeprom_93xx46_write;
534 	edev->nvmem_config.priv = edev;
535 	edev->nvmem_config.stride = 4;
536 	edev->nvmem_config.word_size = 1;
537 	edev->nvmem_config.size = edev->size;
539 	edev->nvmem = devm_nvmem_register(&spi->dev, &edev->nvmem_config);
540 	if (IS_ERR(edev->nvmem))
541 		return PTR_ERR(edev->nvmem);
545 		edev->size,
553 	spi_set_drvdata(spi, edev);
559 	struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi);
561 	if (!(edev->pdata->flags & EE_READONLY))