Lines Matching refs:afu
89 #define AFUD_READ(afu, off) in_be64(afu->native->afu_desc_mmio + off)
90 #define AFUD_READ_LE(afu, off) in_le64(afu->native->afu_desc_mmio + off)
94 #define AFUD_READ_INFO(afu) AFUD_READ(afu, 0x0)
103 #define AFUD_READ_CR(afu) AFUD_READ(afu, 0x20)
105 #define AFUD_READ_CR_OFF(afu) AFUD_READ(afu, 0x28)
106 #define AFUD_READ_PPPSA(afu) AFUD_READ(afu, 0x30)
110 #define AFUD_READ_PPPSA_OFF(afu) AFUD_READ(afu, 0x38)
111 #define AFUD_READ_EB(afu) AFUD_READ(afu, 0x40)
113 #define AFUD_READ_EB_OFF(afu) AFUD_READ(afu, 0x48)
259 static void dump_afu_descriptor(struct cxl_afu *afu)
265 dev_info(&afu->dev, "afu desc: %30s: %#llx\n", name, what)
267 val = AFUD_READ_INFO(afu);
274 val = AFUD_READ(afu, 0x8);
276 val = AFUD_READ(afu, 0x10);
278 val = AFUD_READ(afu, 0x18);
281 val = AFUD_READ_CR(afu);
286 val = AFUD_READ_CR_OFF(afu);
290 val = AFUD_READ_PPPSA(afu);
294 val = AFUD_READ_PPPSA_OFF(afu);
297 val = AFUD_READ_EB(afu);
301 val = AFUD_READ_EB_OFF(afu);
305 val = AFUD_READ_LE(afu, afu_cr_off + i * afu_cr_len);
629 static int init_implementation_afu_regs_psl9(struct cxl_afu *afu)
634 static int init_implementation_afu_regs_psl8(struct cxl_afu *afu)
637 cxl_p1n_write(afu, CXL_PSL_APCALLOC_A, 0xFFFFFFFEFEFEFEFEULL);
639 cxl_p1n_write(afu, CXL_PSL_COALLOC_A, 0xFF000000FEFEFEFEULL);
641 cxl_p1n_write(afu, CXL_PSL_SLICE_TRACE, 0x0000FFFF00000000ULL);
642 cxl_p1n_write(afu, CXL_PSL_RXCTL_A, CXL_PSL_RXCTL_AFUHP_4S);
774 static int pci_map_slice_regs(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
780 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size);
781 p2n_base = p2_base(dev) + (afu->slice * p2n_size);
782 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size));
783 afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_size);
785 if (!(afu->native->p1n_mmio = ioremap(p1n_base, p1n_size)))
787 if (!(afu->p2n_mmio = ioremap(p2n_base, p2n_size)))
790 if (!(afu->native->afu_desc_mmio = ioremap(afu_desc, adapter->native->afu_desc_size)))
796 iounmap(afu->p2n_mmio);
798 iounmap(afu->native->p1n_mmio);
800 dev_err(&afu->dev, "Error mapping AFU MMIO regions\n");
804 static void pci_unmap_slice_regs(struct cxl_afu *afu)
806 if (afu->p2n_mmio) {
807 iounmap(afu->p2n_mmio);
808 afu->p2n_mmio = NULL;
810 if (afu->native->p1n_mmio) {
811 iounmap(afu->native->p1n_mmio);
812 afu->native->p1n_mmio = NULL;
814 if (afu->native->afu_desc_mmio) {
815 iounmap(afu->native->afu_desc_mmio);
816 afu->native->afu_desc_mmio = NULL;
822 struct cxl_afu *afu = to_cxl_afu(dev);
826 idr_destroy(&afu->contexts_idr);
827 cxl_release_spa(afu);
829 kfree(afu->native);
830 kfree(afu);
834 static int cxl_read_afu_descriptor(struct cxl_afu *afu)
838 val = AFUD_READ_INFO(afu);
839 afu->pp_irqs = AFUD_NUM_INTS_PER_PROC(val);
840 afu->max_procs_virtualised = AFUD_NUM_PROCS(val);
841 afu->crs_num = AFUD_NUM_CRS(val);
844 afu->modes_supported |= CXL_MODE_DIRECTED;
846 afu->modes_supported |= CXL_MODE_DEDICATED;
848 afu->modes_supported |= CXL_MODE_TIME_SLICED;
850 val = AFUD_READ_PPPSA(afu);
851 afu->pp_size = AFUD_PPPSA_LEN(val) * 4096;
852 afu->psa = AFUD_PPPSA_PSA(val);
853 if ((afu->pp_psa = AFUD_PPPSA_PP(val)))
854 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu);
856 val = AFUD_READ_CR(afu);
857 afu->crs_len = AFUD_CR_LEN(val) * 256;
858 afu->crs_offset = AFUD_READ_CR_OFF(afu);
862 afu->eb_len = AFUD_EB_LEN(AFUD_READ_EB(afu)) * 4096;
863 afu->eb_offset = AFUD_READ_EB_OFF(afu);
866 if (EXTRACT_PPC_BITS(afu->eb_offset, 0, 11) != 0) {
867 dev_warn(&afu->dev,
869 afu->eb_offset);
870 dev_info(&afu->dev,
872 /* indicate that no afu buffer exists */
873 afu->eb_len = 0;
879 static int cxl_afu_descriptor_looks_ok(struct cxl_afu *afu)
884 if (afu->psa && afu->adapter->ps_size <
885 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) {
886 dev_err(&afu->dev, "per-process PSA can't fit inside the PSA!\n");
890 if (afu->pp_psa && (afu->pp_size < PAGE_SIZE))
891 dev_warn(&afu->dev, "AFU uses pp_size(%#016llx) < PAGE_SIZE per-process PSA!\n", afu->pp_size);
893 for (i = 0; i < afu->crs_num; i++) {
894 rc = cxl_ops->afu_cr_read32(afu, i, 0, &val);
896 dev_err(&afu->dev, "ABORTING: AFU configuration record %i is invalid\n", i);
901 if ((afu->modes_supported & ~CXL_MODE_DEDICATED) && afu->max_procs_virtualised == 0) {
912 dev_err(&afu->dev, "AFU does not support any processes\n");
919 static int sanitise_afu_regs_psl9(struct cxl_afu *afu)
928 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
930 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
931 if (cxl_ops->afu_reset(afu))
933 if (cxl_afu_disable(afu))
935 if (cxl_psl_purge(afu))
938 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
939 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
940 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
942 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
944 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
946 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
948 if (afu->adapter->native->sl_ops->register_serr_irq) {
949 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
952 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
953 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
956 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
958 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
959 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
965 static int sanitise_afu_regs_psl8(struct cxl_afu *afu)
974 reg = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
976 dev_warn(&afu->dev, "WARNING: AFU was not disabled: %#016llx\n", reg);
977 if (cxl_ops->afu_reset(afu))
979 if (cxl_afu_disable(afu))
981 if (cxl_psl_purge(afu))
984 cxl_p1n_write(afu, CXL_PSL_SPAP_An, 0x0000000000000000);
985 cxl_p1n_write(afu, CXL_PSL_IVTE_Limit_An, 0x0000000000000000);
986 cxl_p1n_write(afu, CXL_PSL_IVTE_Offset_An, 0x0000000000000000);
987 cxl_p1n_write(afu, CXL_PSL_AMBAR_An, 0x0000000000000000);
988 cxl_p1n_write(afu, CXL_PSL_SPOffset_An, 0x0000000000000000);
989 cxl_p1n_write(afu, CXL_HAURP_An, 0x0000000000000000);
990 cxl_p2n_write(afu, CXL_CSRP_An, 0x0000000000000000);
991 cxl_p2n_write(afu, CXL_AURP1_An, 0x0000000000000000);
992 cxl_p2n_write(afu, CXL_AURP0_An, 0x0000000000000000);
993 cxl_p2n_write(afu, CXL_SSTP1_An, 0x0000000000000000);
994 cxl_p2n_write(afu, CXL_SSTP0_An, 0x0000000000000000);
995 reg = cxl_p2n_read(afu, CXL_PSL_DSISR_An);
997 dev_warn(&afu->dev, "AFU had pending DSISR: %#016llx\n", reg);
999 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_AE);
1001 cxl_p2n_write(afu, CXL_PSL_TFC_An, CXL_PSL_TFC_An_A);
1003 if (afu->adapter->native->sl_ops->register_serr_irq) {
1004 reg = cxl_p1n_read(afu, CXL_PSL_SERR_An);
1007 dev_warn(&afu->dev, "AFU had pending SERR: %#016llx\n", reg);
1008 cxl_p1n_write(afu, CXL_PSL_SERR_An, reg & ~0xffff);
1011 reg = cxl_p2n_read(afu, CXL_PSL_ErrStat_An);
1013 dev_warn(&afu->dev, "AFU had pending error status: %#016llx\n", reg);
1014 cxl_p2n_write(afu, CXL_PSL_ErrStat_An, reg);
1023 * Called from sysfs and reads the afu error info buffer. The h/w only supports
1027 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
1033 const void __iomem *ebuf = afu->native->afu_desc_mmio + afu->eb_offset;
1035 if (count == 0 || off < 0 || (size_t)off >= afu->eb_len)
1039 count = min((size_t)(afu->eb_len - off), count);
1064 static int pci_configure_afu(struct cxl_afu *afu, struct cxl *adapter, struct pci_dev *dev)
1068 if ((rc = pci_map_slice_regs(afu, adapter, dev)))
1072 rc = adapter->native->sl_ops->sanitise_afu_regs(afu);
1078 if ((rc = cxl_ops->afu_reset(afu)))
1082 dump_afu_descriptor(afu);
1084 if ((rc = cxl_read_afu_descriptor(afu)))
1087 if ((rc = cxl_afu_descriptor_looks_ok(afu)))
1091 if ((rc = adapter->native->sl_ops->afu_regs_init(afu)))
1095 if ((rc = adapter->native->sl_ops->register_serr_irq(afu)))
1098 if ((rc = cxl_native_register_psl_irq(afu)))
1101 atomic_set(&afu->configured_state, 0);
1106 adapter->native->sl_ops->release_serr_irq(afu);
1108 pci_unmap_slice_regs(afu);
1112 static void pci_deconfigure_afu(struct cxl_afu *afu)
1118 if (atomic_read(&afu->configured_state) != -1) {
1119 while (atomic_cmpxchg(&afu->configured_state, 0, -1) != -1)
1122 cxl_native_release_psl_irq(afu);
1123 if (afu->adapter->native->sl_ops->release_serr_irq)
1124 afu->adapter->native->sl_ops->release_serr_irq(afu);
1125 pci_unmap_slice_regs(afu);
1130 struct cxl_afu *afu;
1133 afu = cxl_alloc_afu(adapter, slice);
1134 if (!afu)
1137 afu->native = kzalloc(sizeof(struct cxl_afu_native), GFP_KERNEL);
1138 if (!afu->native)
1141 mutex_init(&afu->native->spa_mutex);
1143 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice);
1147 rc = pci_configure_afu(afu, adapter, dev);
1152 cxl_debugfs_afu_add(afu);
1155 * After we call this function we must not free the afu directly, even
1158 if ((rc = cxl_register_afu(afu)))
1161 if ((rc = cxl_sysfs_afu_add(afu)))
1164 adapter->afu[afu->slice] = afu;
1166 if ((rc = cxl_pci_vphb_add(afu)))
1167 dev_info(&afu->dev, "Can't register vPHB\n");
1172 device_del(&afu->dev);
1174 pci_deconfigure_afu(afu);
1175 cxl_debugfs_afu_remove(afu);
1176 put_device(&afu->dev);
1180 kfree(afu->native);
1182 kfree(afu);
1187 static void cxl_pci_remove_afu(struct cxl_afu *afu)
1191 if (!afu)
1194 cxl_pci_vphb_remove(afu);
1195 cxl_sysfs_afu_remove(afu);
1196 cxl_debugfs_afu_remove(afu);
1198 spin_lock(&afu->adapter->afu_list_lock);
1199 afu->adapter->afu[afu->slice] = NULL;
1200 spin_unlock(&afu->adapter->afu_list_lock);
1202 cxl_context_detach_all(afu);
1203 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1205 pci_deconfigure_afu(afu);
1206 device_unregister(&afu->dev);
1561 if (adapter->afu[slice])
1562 cxl_p1n_write(adapter->afu[slice], CXL_PSL_SLICE_TRACE,
1765 rc = cxl_afu_select_best_mode(adapter->afu[slice]);
1776 struct cxl_afu *afu;
1784 afu = adapter->afu[i];
1785 cxl_pci_remove_afu(afu);
1790 static pci_ers_result_t cxl_vphb_error_detected(struct cxl_afu *afu,
1802 if (afu == NULL || afu->phb == NULL)
1805 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
1830 struct cxl_afu *afu;
1845 afu = adapter->afu[i];
1850 cxl_vphb_error_detected(afu, state);
1935 /* Make sure no one else changes the afu list */
1939 afu = adapter->afu[i];
1941 if (afu == NULL)
1944 afu_result = cxl_vphb_error_detected(afu, state);
1945 cxl_context_detach_all(afu);
1946 cxl_ops->afu_deactivate_mode(afu, afu->current_mode);
1947 pci_deconfigure_afu(afu);
1972 struct cxl_afu *afu;
1993 afu = adapter->afu[i];
1995 if (afu == NULL)
1998 if (pci_configure_afu(afu, adapter, pdev))
2001 if (cxl_afu_select_best_mode(afu))
2004 if (afu->phb == NULL)
2007 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {
2022 if (cxl_ops->afu_check_and_enable(afu))
2064 struct cxl_afu *afu;
2076 afu = adapter->afu[i];
2078 if (afu == NULL || afu->phb == NULL)
2081 list_for_each_entry(afu_dev, &afu->phb->bus->devices, bus_list) {