Lines Matching defs:dsisr
26 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar)
28 ctx->dsisr = dsisr;
36 u64 dsisr, dar;
38 dsisr = irq_info->dsisr;
41 trace_cxl_psl9_irq(ctx, irq, dsisr, dar);
43 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
45 if (dsisr & CXL_PSL9_DSISR_An_TF) {
47 return schedule_cxl_fault(ctx, dsisr, dar);
50 if (dsisr & CXL_PSL9_DSISR_An_PE)
51 return cxl_ops->handle_psl_slice_error(ctx, dsisr,
53 if (dsisr & CXL_PSL9_DSISR_An_AE) {
78 if (dsisr & CXL_PSL9_DSISR_An_OC)
87 u64 dsisr, dar;
89 dsisr = irq_info->dsisr;
92 trace_cxl_psl_irq(ctx, irq, dsisr, dar);
94 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar);
96 if (dsisr & CXL_PSL_DSISR_An_DS) {
108 return schedule_cxl_fault(ctx, dsisr, dar);
111 if (dsisr & CXL_PSL_DSISR_An_M)
113 if (dsisr & CXL_PSL_DSISR_An_P)
115 if (dsisr & CXL_PSL_DSISR_An_A)
117 if (dsisr & CXL_PSL_DSISR_An_S)
119 if (dsisr & CXL_PSL_DSISR_An_K)
122 if (dsisr & CXL_PSL_DSISR_An_DM) {
129 return schedule_cxl_fault(ctx, dsisr, dar);
131 if (dsisr & CXL_PSL_DSISR_An_ST)
133 if (dsisr & CXL_PSL_DSISR_An_UR)
135 if (dsisr & CXL_PSL_DSISR_An_PE)
136 return cxl_ops->handle_psl_slice_error(ctx, dsisr,
138 if (dsisr & CXL_PSL_DSISR_An_AE) {
164 if (dsisr & CXL_PSL_DSISR_An_OC)