Lines Matching refs:pcr
64 static int rtsx_comm_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
66 rtsx_pci_write_register(pcr, MSGTXDATA0,
68 rtsx_pci_write_register(pcr, MSGTXDATA1,
70 rtsx_pci_write_register(pcr, MSGTXDATA2,
72 rtsx_pci_write_register(pcr, MSGTXDATA3,
74 rtsx_pci_write_register(pcr, LTR_CTL, LTR_TX_EN_MASK |
80 int rtsx_set_ltr_latency(struct rtsx_pcr *pcr, u32 latency)
82 return rtsx_comm_set_ltr_latency(pcr, latency);
85 static void rtsx_comm_set_aspm(struct rtsx_pcr *pcr, bool enable)
87 if (pcr->aspm_enabled == enable)
90 if (pcr->aspm_mode == ASPM_MODE_CFG) {
91 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
93 enable ? pcr->aspm_en : 0);
94 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
95 if (pcr->aspm_en & 0x02)
96 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
99 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, FORCE_ASPM_CTL0 |
103 if (!enable && (pcr->aspm_en & 0x02))
106 pcr->aspm_enabled = enable;
109 static void rtsx_disable_aspm(struct rtsx_pcr *pcr)
111 if (pcr->ops->set_aspm)
112 pcr->ops->set_aspm(pcr, false);
114 rtsx_comm_set_aspm(pcr, false);
117 int rtsx_set_l1off_sub(struct rtsx_pcr *pcr, u8 val)
119 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, val);
124 static void rtsx_set_l1off_sub_cfg_d0(struct rtsx_pcr *pcr, int active)
126 if (pcr->ops->set_l1off_cfg_sub_d0)
127 pcr->ops->set_l1off_cfg_sub_d0(pcr, active);
130 static void rtsx_comm_pm_full_on(struct rtsx_pcr *pcr)
132 struct rtsx_cr_option *option = &pcr->option;
134 rtsx_disable_aspm(pcr);
140 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
142 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
143 rtsx_set_l1off_sub_cfg_d0(pcr, 1);
146 static void rtsx_pm_full_on(struct rtsx_pcr *pcr)
148 rtsx_comm_pm_full_on(pcr);
151 void rtsx_pci_start_run(struct rtsx_pcr *pcr)
154 if (pcr->remove_pci)
157 if (pcr->state != PDEV_STAT_RUN) {
158 pcr->state = PDEV_STAT_RUN;
159 if (pcr->ops->enable_auto_blink)
160 pcr->ops->enable_auto_blink(pcr);
161 rtsx_pm_full_on(pcr);
166 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data)
175 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
178 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
190 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data)
196 rtsx_pci_writel(pcr, RTSX_HAIMR, val);
199 val = rtsx_pci_readl(pcr, RTSX_HAIMR);
214 int __rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
219 rtsx_pci_write_register(pcr, PHYDATA0, 0xFF, (u8)val);
220 rtsx_pci_write_register(pcr, PHYDATA1, 0xFF, (u8)(val >> 8));
221 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
222 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x81);
225 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
241 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val)
243 if (pcr->ops->write_phy)
244 return pcr->ops->write_phy(pcr, addr, val);
246 return __rtsx_pci_write_phy_register(pcr, addr, val);
250 int __rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
256 rtsx_pci_write_register(pcr, PHYADDR, 0xFF, addr);
257 rtsx_pci_write_register(pcr, PHYRWCTL, 0xFF, 0x80);
260 err = rtsx_pci_read_register(pcr, PHYRWCTL, &tmp);
273 rtsx_pci_read_register(pcr, PHYDATA0, &val1);
274 rtsx_pci_read_register(pcr, PHYDATA1, &val2);
283 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val)
285 if (pcr->ops->read_phy)
286 return pcr->ops->read_phy(pcr, addr, val);
288 return __rtsx_pci_read_phy_register(pcr, addr, val);
292 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr)
294 if (pcr->ops->stop_cmd)
295 return pcr->ops->stop_cmd(pcr);
297 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
298 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
300 rtsx_pci_write_register(pcr, DMACTL, 0x80, 0x80);
301 rtsx_pci_write_register(pcr, RBCTL, 0x80, 0x80);
305 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
310 u32 *ptr = (u32 *)(pcr->host_cmds_ptr);
317 spin_lock_irqsave(&pcr->lock, flags);
318 ptr += pcr->ci;
319 if (pcr->ci < (HOST_CMDS_BUF_LEN / 4)) {
322 pcr->ci++;
324 spin_unlock_irqrestore(&pcr->lock, flags);
328 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr)
332 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
334 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
337 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
341 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout)
349 spin_lock_irqsave(&pcr->lock, flags);
352 pcr->done = &trans_done;
353 pcr->trans_result = TRANS_NOT_READY;
356 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
358 val |= (u32)(pcr->ci * 4) & 0x00FFFFFF;
361 rtsx_pci_writel(pcr, RTSX_HCBCTLR, val);
363 spin_unlock_irqrestore(&pcr->lock, flags);
369 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
374 spin_lock_irqsave(&pcr->lock, flags);
375 if (pcr->trans_result == TRANS_RESULT_FAIL)
377 else if (pcr->trans_result == TRANS_RESULT_OK)
379 else if (pcr->trans_result == TRANS_NO_DEVICE)
381 spin_unlock_irqrestore(&pcr->lock, flags);
384 spin_lock_irqsave(&pcr->lock, flags);
385 pcr->done = NULL;
386 spin_unlock_irqrestore(&pcr->lock, flags);
389 rtsx_pci_stop_cmd(pcr);
391 if (pcr->finish_me)
392 complete(pcr->finish_me);
398 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr *pcr,
401 u64 *ptr = (u64 *)(pcr->host_sg_tbl_ptr) + pcr->sgi;
405 pcr_dbg(pcr, "DMA addr: 0x%x, Len: 0x%x\n", (unsigned int)addr, len);
410 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5228)) {
420 pcr->sgi++;
423 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
428 pcr_dbg(pcr, "--> %s: num_sg = %d\n", __func__, num_sg);
429 count = rtsx_pci_dma_map_sg(pcr, sglist, num_sg, read);
432 pcr_dbg(pcr, "DMA mapping count: %d\n", count);
434 err = rtsx_pci_dma_transfer(pcr, sglist, count, read, timeout);
436 rtsx_pci_dma_unmap_sg(pcr, sglist, num_sg, read);
442 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
447 if (pcr->remove_pci)
453 return dma_map_sg(&(pcr->pci->dev), sglist, num_sg, dir);
457 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
462 dma_unmap_sg(&(pcr->pci->dev), sglist, num_sg, dir);
466 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
479 if (pcr->remove_pci)
486 pcr->sgi = 0;
490 rtsx_pci_add_sg_tbl(pcr, addr, len, i == count - 1);
493 spin_lock_irqsave(&pcr->lock, flags);
495 pcr->done = &trans_done;
496 pcr->trans_result = TRANS_NOT_READY;
498 rtsx_pci_writel(pcr, RTSX_HDBAR, pcr->host_sg_tbl_addr);
499 rtsx_pci_writel(pcr, RTSX_HDBCTLR, val);
501 spin_unlock_irqrestore(&pcr->lock, flags);
506 pcr_dbg(pcr, "Timeout (%s %d)\n", __func__, __LINE__);
511 spin_lock_irqsave(&pcr->lock, flags);
512 if (pcr->trans_result == TRANS_RESULT_FAIL) {
514 if (pcr->dma_error_count < RTS_MAX_TIMES_FREQ_REDUCTION)
515 pcr->dma_error_count++;
518 else if (pcr->trans_result == TRANS_NO_DEVICE)
520 spin_unlock_irqrestore(&pcr->lock, flags);
523 spin_lock_irqsave(&pcr->lock, flags);
524 pcr->done = NULL;
525 spin_unlock_irqrestore(&pcr->lock, flags);
528 rtsx_pci_stop_cmd(pcr);
530 if (pcr->finish_me)
531 complete(pcr->finish_me);
537 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
550 rtsx_pci_init_cmd(pcr);
553 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
555 err = rtsx_pci_send_cmd(pcr, 250);
559 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), 256);
564 rtsx_pci_init_cmd(pcr);
567 rtsx_pci_add_cmd(pcr, READ_REG_CMD, reg++, 0, 0);
569 err = rtsx_pci_send_cmd(pcr, 250);
574 memcpy(ptr, rtsx_pci_get_cmd_data(pcr), buf_len % 256);
580 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len)
593 rtsx_pci_init_cmd(pcr);
596 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
601 err = rtsx_pci_send_cmd(pcr, 250);
607 rtsx_pci_init_cmd(pcr);
610 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
615 err = rtsx_pci_send_cmd(pcr, 250);
624 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr *pcr, const u32 *tbl)
626 rtsx_pci_init_cmd(pcr);
629 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
634 return rtsx_pci_send_cmd(pcr, 100);
637 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card)
642 tbl = pcr->sd_pull_ctl_enable_tbl;
644 tbl = pcr->ms_pull_ctl_enable_tbl;
648 return rtsx_pci_set_pull_ctl(pcr, tbl);
652 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card)
657 tbl = pcr->sd_pull_ctl_disable_tbl;
659 tbl = pcr->ms_pull_ctl_disable_tbl;
663 return rtsx_pci_set_pull_ctl(pcr, tbl);
667 static void rtsx_pci_enable_bus_int(struct rtsx_pcr *pcr)
669 struct rtsx_hw_param *hw_param = &pcr->hw_param;
671 pcr->bier = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN | SD_INT_EN
674 if (pcr->num_slots > 1)
675 pcr->bier |= MS_INT_EN;
678 rtsx_pci_writel(pcr, RTSX_BIER, pcr->bier);
680 pcr_dbg(pcr, "RTSX_BIER: 0x%08x\n", pcr->bier);
700 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
713 if (PCI_PID(pcr) == PID_5261)
714 return rts5261_pci_switch_clock(pcr, card_clock,
716 if (PCI_PID(pcr) == PID_5228)
717 return rts5228_pci_switch_clock(pcr, card_clock,
719 if (PCI_PID(pcr) == PID_5264)
720 return rts5264_pci_switch_clock(pcr, card_clock,
730 err = rtsx_pci_write_register(pcr, SD_CFG1,
737 pcr->dma_error_count &&
738 PCI_PID(pcr) == RTS5227_DEVICE_ID)
740 (pcr->dma_error_count * 20000000);
743 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock);
748 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
749 clk, pcr->cur_clock);
751 if (clk == pcr->cur_clock)
754 if (pcr->ops->conv_clk_and_div_n)
755 n = (u8)pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N);
768 if (pcr->ops->conv_clk_and_div_n) {
769 int dbl_clk = pcr->ops->conv_clk_and_div_n(n,
771 n = (u8)pcr->ops->conv_clk_and_div_n(dbl_clk,
778 pcr_dbg(pcr, "n = %d, div = %d\n", n, div);
785 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth);
787 rtsx_pci_init_cmd(pcr);
788 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL,
790 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV,
792 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
793 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2,
795 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
796 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
798 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
800 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL,
804 err = rtsx_pci_send_cmd(pcr, 2000);
810 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
814 pcr->cur_clock = clk;
819 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card)
821 if (pcr->ops->card_power_on)
822 return pcr->ops->card_power_on(pcr, card);
828 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card)
830 if (pcr->ops->card_power_off)
831 return pcr->ops->card_power_off(pcr, card);
837 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card)
844 if (!(pcr->flags & PCR_MS_PMOS)) {
848 if (pcr->card_exist & (~cd_mask[card]))
856 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
858 if (pcr->ops->switch_output_voltage)
859 return pcr->ops->switch_output_voltage(pcr, voltage);
865 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr)
869 val = rtsx_pci_readl(pcr, RTSX_BIPR);
870 if (pcr->ops->cd_deglitch)
871 val = pcr->ops->cd_deglitch(pcr);
877 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr)
881 pcr->finish_me = &finish;
884 if (pcr->done)
885 complete(pcr->done);
887 if (!pcr->remove_pci)
888 rtsx_pci_stop_cmd(pcr);
892 pcr->finish_me = NULL;
899 struct rtsx_pcr *pcr;
905 pcr = container_of(dwork, struct rtsx_pcr, carddet_work);
907 pcr_dbg(pcr, "--> %s\n", __func__);
909 mutex_lock(&pcr->pcr_mutex);
910 spin_lock_irqsave(&pcr->lock, flags);
912 irq_status = rtsx_pci_readl(pcr, RTSX_BIPR);
913 pcr_dbg(pcr, "irq_status: 0x%08x\n", irq_status);
916 card_inserted = pcr->card_inserted & irq_status;
917 card_removed = pcr->card_removed;
918 pcr->card_inserted = 0;
919 pcr->card_removed = 0;
921 spin_unlock_irqrestore(&pcr->lock, flags);
924 pcr_dbg(pcr, "card_inserted: 0x%x, card_removed: 0x%x\n",
927 if (pcr->ops->cd_deglitch)
928 card_inserted = pcr->ops->cd_deglitch(pcr);
932 pcr->card_exist |= card_inserted;
933 pcr->card_exist &= ~card_removed;
936 mutex_unlock(&pcr->pcr_mutex);
938 if ((card_detect & SD_EXIST) && pcr->slots[RTSX_SD_CARD].card_event)
939 pcr->slots[RTSX_SD_CARD].card_event(
940 pcr->slots[RTSX_SD_CARD].p_dev);
941 if ((card_detect & MS_EXIST) && pcr->slots[RTSX_MS_CARD].card_event)
942 pcr->slots[RTSX_MS_CARD].card_event(
943 pcr->slots[RTSX_MS_CARD].p_dev);
946 static void rtsx_pci_process_ocp(struct rtsx_pcr *pcr)
948 if (pcr->ops->process_ocp) {
949 pcr->ops->process_ocp(pcr);
951 if (!pcr->option.ocp_en)
953 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
954 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
955 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
956 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
957 rtsx_pci_clear_ocpstat(pcr);
958 pcr->ocp_stat = 0;
963 static int rtsx_pci_process_ocp_interrupt(struct rtsx_pcr *pcr)
965 if (pcr->option.ocp_en)
966 rtsx_pci_process_ocp(pcr);
973 struct rtsx_pcr *pcr = dev_id;
976 if (!pcr)
979 spin_lock(&pcr->lock);
981 int_reg = rtsx_pci_readl(pcr, RTSX_BIPR);
983 rtsx_pci_writel(pcr, RTSX_BIPR, int_reg);
984 if ((int_reg & pcr->bier) == 0) {
985 spin_unlock(&pcr->lock);
989 spin_unlock(&pcr->lock);
993 int_reg &= (pcr->bier | 0x7FFFFF);
996 ((int_reg & SD_OVP_INT) && (PCI_PID(pcr) == PID_5264)))
997 rtsx_pci_process_ocp_interrupt(pcr);
1001 pcr->card_inserted |= SD_EXIST;
1003 pcr->card_removed |= SD_EXIST;
1004 pcr->card_inserted &= ~SD_EXIST;
1005 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {
1006 rtsx_pci_write_register(pcr, RTS5261_FW_STATUS,
1008 pcr->extra_caps |= EXTRA_CAPS_SD_EXPRESS;
1011 pcr->dma_error_count = 0;
1016 pcr->card_inserted |= MS_EXIST;
1018 pcr->card_removed |= MS_EXIST;
1019 pcr->card_inserted &= ~MS_EXIST;
1025 pcr->trans_result = TRANS_RESULT_FAIL;
1026 if (pcr->done)
1027 complete(pcr->done);
1029 pcr->trans_result = TRANS_RESULT_OK;
1030 if (pcr->done)
1031 complete(pcr->done);
1035 if ((pcr->card_inserted || pcr->card_removed) && !(int_reg & SD_OC_INT))
1036 schedule_delayed_work(&pcr->carddet_work,
1039 spin_unlock(&pcr->lock);
1043 static int rtsx_pci_acquire_irq(struct rtsx_pcr *pcr)
1045 pcr_dbg(pcr, "%s: pcr->msi_en = %d, pci->irq = %d\n",
1046 __func__, pcr->msi_en, pcr->pci->irq);
1048 if (request_irq(pcr->pci->irq, rtsx_pci_isr,
1049 pcr->msi_en ? 0 : IRQF_SHARED,
1050 DRV_NAME_RTSX_PCI, pcr)) {
1051 dev_err(&(pcr->pci->dev),
1053 pcr->pci->irq);
1057 pcr->irq = pcr->pci->irq;
1058 pci_intx(pcr->pci, !pcr->msi_en);
1063 static void rtsx_base_force_power_down(struct rtsx_pcr *pcr)
1066 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
1067 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
1068 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
1071 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3,
1074 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
1077 static void __maybe_unused rtsx_pci_power_off(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
1079 if (pcr->ops->turn_off_led)
1080 pcr->ops->turn_off_led(pcr);
1082 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1083 pcr->bier = 0;
1085 rtsx_pci_write_register(pcr, PETXCFG, 0x08, 0x08);
1086 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, pm_state);
1088 if (pcr->ops->force_power_down)
1089 pcr->ops->force_power_down(pcr, pm_state, runtime);
1091 rtsx_base_force_power_down(pcr);
1094 void rtsx_pci_enable_ocp(struct rtsx_pcr *pcr)
1098 if (pcr->ops->enable_ocp) {
1099 pcr->ops->enable_ocp(pcr);
1101 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1102 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
1107 void rtsx_pci_disable_ocp(struct rtsx_pcr *pcr)
1111 if (pcr->ops->disable_ocp) {
1112 pcr->ops->disable_ocp(pcr);
1114 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1115 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
1120 void rtsx_pci_init_ocp(struct rtsx_pcr *pcr)
1122 if (pcr->ops->init_ocp) {
1123 pcr->ops->init_ocp(pcr);
1125 struct rtsx_cr_option *option = &(pcr->option);
1130 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN, 0);
1131 rtsx_pci_write_register(pcr, REG_OCPPARA1,
1133 rtsx_pci_write_register(pcr, REG_OCPPARA2,
1135 rtsx_pci_write_register(pcr, REG_OCPGLITCH,
1136 SD_OCP_GLITCH_MASK, pcr->hw_param.ocp_glitch);
1137 rtsx_pci_enable_ocp(pcr);
1142 int rtsx_pci_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
1144 if (pcr->ops->get_ocpstat)
1145 return pcr->ops->get_ocpstat(pcr, val);
1147 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
1150 void rtsx_pci_clear_ocpstat(struct rtsx_pcr *pcr)
1152 if (pcr->ops->clear_ocpstat) {
1153 pcr->ops->clear_ocpstat(pcr);
1158 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
1160 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
1164 void rtsx_pci_enable_oobs_polling(struct rtsx_pcr *pcr)
1168 if ((PCI_PID(pcr) != PID_525A) &&
1169 (PCI_PID(pcr) != PID_5260) &&
1170 (PCI_PID(pcr) != PID_5264)) {
1171 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1173 rtsx_pci_write_phy_register(pcr, 0x01, val);
1175 rtsx_pci_write_register(pcr, REG_CFG_OOBS_OFF_TIMER, 0xFF, 0x32);
1176 rtsx_pci_write_register(pcr, REG_CFG_OOBS_ON_TIMER, 0xFF, 0x05);
1177 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x83);
1178 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0xDE);
1182 void rtsx_pci_disable_oobs_polling(struct rtsx_pcr *pcr)
1186 if ((PCI_PID(pcr) != PID_525A) &&
1187 (PCI_PID(pcr) != PID_5260) &&
1188 (PCI_PID(pcr) != PID_5264)) {
1189 rtsx_pci_read_phy_register(pcr, 0x01, &val);
1191 rtsx_pci_write_phy_register(pcr, 0x01, val);
1193 rtsx_pci_write_register(pcr, REG_CFG_VCM_ON_TIMER, 0xFF, 0x03);
1194 rtsx_pci_write_register(pcr, REG_CFG_OOBS_POLLING, 0xFF, 0x00);
1198 int rtsx_sd_power_off_card3v3(struct rtsx_pcr *pcr)
1200 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1202 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
1203 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
1207 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD);
1212 int rtsx_ms_power_off_card3v3(struct rtsx_pcr *pcr)
1214 rtsx_pci_write_register(pcr, CARD_CLK_EN, SD_CLK_EN |
1217 rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
1219 rtsx_pci_write_register(pcr, CARD_OE, MS_OUTPUT_EN, 0);
1220 rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
1225 static int rtsx_pci_init_hw(struct rtsx_pcr *pcr)
1227 struct pci_dev *pdev = pcr->pci;
1230 if (PCI_PID(pcr) == PID_5228)
1231 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, RTS5228_LDO1_SR_TIME_MASK,
1234 rtsx_pci_writel(pcr, RTSX_HCBAR, pcr->host_cmds_addr);
1236 rtsx_pci_enable_bus_int(pcr);
1239 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) {
1241 err = rtsx_pci_write_register(pcr, RTS5261_FW_CFG1,
1243 err = rtsx_pci_write_register(pcr, RTS5261_REG_FPDCTL,
1246 err = rtsx_pci_write_register(pcr, FPDCTL, SSC_POWER_DOWN, 0);
1254 rtsx_disable_aspm(pcr);
1255 if (pcr->ops->optimize_phy) {
1256 err = pcr->ops->optimize_phy(pcr);
1261 rtsx_pci_init_cmd(pcr);
1264 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07);
1266 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, HOST_SLEEP_STATE, 0x03, 0x00);
1268 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 0x1E, 0);
1270 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x0A, 0);
1272 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DRIVE_SEL,
1273 0xFF, pcr->card_drive_sel);
1275 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1,
1277 if (PCI_PID(pcr) == PID_5261)
1278 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1280 else if (PCI_PID(pcr) == PID_5228)
1281 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1283 else if (is_version(pcr, 0x5264, IC_VER_A))
1284 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
1285 else if (PCI_PID(pcr) == PID_5264)
1286 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF,
1289 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 0xFF, 0x12);
1292 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CHANGE_LINK_STATE, 0x16, 0x10);
1294 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
1299 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PERST_GLITCH_WIDTH, 0xFF, 0x80);
1304 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RCCTL, 0x01, 0x00);
1310 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, NFTS_TX_CTRL, 0x02, 0);
1312 err = rtsx_pci_send_cmd(pcr, 100);
1316 switch (PCI_PID(pcr)) {
1324 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 1, 1);
1331 rtsx_pci_init_ocp(pcr);
1334 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL,
1339 if (pcr->ops->extra_init_hw) {
1340 err = pcr->ops->extra_init_hw(pcr);
1345 if (pcr->aspm_mode == ASPM_MODE_REG)
1346 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0x30, 0x30);
1349 * So we need to initialize pcr->card_exist here.
1351 if (pcr->ops->cd_deglitch)
1352 pcr->card_exist = pcr->ops->cd_deglitch(pcr);
1354 pcr->card_exist = rtsx_pci_readl(pcr, RTSX_BIPR) & CARD_EXIST;
1359 static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
1361 struct rtsx_cr_option *option = &(pcr->option);
1367 spin_lock_init(&pcr->lock);
1368 mutex_init(&pcr->pcr_mutex);
1370 switch (PCI_PID(pcr)) {
1373 rts5209_init_params(pcr);
1377 rts5229_init_params(pcr);
1381 rtl8411_init_params(pcr);
1385 rts5227_init_params(pcr);
1389 rts522a_init_params(pcr);
1393 rts5249_init_params(pcr);
1397 rts524a_init_params(pcr);
1401 rts525a_init_params(pcr);
1405 rtl8411b_init_params(pcr);
1409 rtl8402_init_params(pcr);
1413 rts5260_init_params(pcr);
1417 rts5261_init_params(pcr);
1421 rts5228_init_params(pcr);
1425 rts5264_init_params(pcr);
1429 pcr_dbg(pcr, "PID: 0x%04x, IC version: 0x%02x\n",
1430 PCI_PID(pcr), pcr->ic_version);
1432 pcr->slots = kcalloc(pcr->num_slots, sizeof(struct rtsx_slot),
1434 if (!pcr->slots)
1437 if (pcr->aspm_mode == ASPM_MODE_CFG) {
1438 pcie_capability_read_word(pcr->pci, PCI_EXP_LNKCTL, &cfg_val);
1440 pcr->aspm_enabled = true;
1442 pcr->aspm_enabled = false;
1444 } else if (pcr->aspm_mode == ASPM_MODE_REG) {
1445 rtsx_pci_read_register(pcr, ASPM_FORCE_CTL, &val);
1447 pcr->aspm_enabled = false;
1449 pcr->aspm_enabled = true;
1452 l1ss = pci_find_ext_capability(pcr->pci, PCI_EXT_CAP_ID_L1SS);
1454 pci_read_config_dword(pcr->pci, l1ss + PCI_L1SS_CTL1, &lval);
1457 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
1459 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
1462 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
1464 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
1467 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
1469 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
1472 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
1474 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
1476 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cfg_val);
1484 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
1494 if (pcr->ops->fetch_vendor_settings)
1495 pcr->ops->fetch_vendor_settings(pcr);
1497 pcr_dbg(pcr, "pcr->aspm_en = 0x%x\n", pcr->aspm_en);
1498 pcr_dbg(pcr, "pcr->sd30_drive_sel_1v8 = 0x%x\n",
1499 pcr->sd30_drive_sel_1v8);
1500 pcr_dbg(pcr, "pcr->sd30_drive_sel_3v3 = 0x%x\n",
1501 pcr->sd30_drive_sel_3v3);
1502 pcr_dbg(pcr, "pcr->card_drive_sel = 0x%x\n",
1503 pcr->card_drive_sel);
1504 pcr_dbg(pcr, "pcr->flags = 0x%x\n", pcr->flags);
1506 pcr->state = PDEV_STAT_IDLE;
1507 err = rtsx_pci_init_hw(pcr);
1509 kfree(pcr->slots);
1519 struct rtsx_pcr *pcr;
1541 pcr = kzalloc(sizeof(*pcr), GFP_KERNEL);
1542 if (!pcr) {
1552 handle->pcr = pcr;
1556 ret = idr_alloc(&rtsx_pci_idr, pcr, 0, 0, GFP_NOWAIT);
1558 pcr->id = ret;
1564 pcr->pci = pcidev;
1567 if ((CHK_PCI_PID(pcr, 0x525A)) || (CHK_PCI_PID(pcr, 0x5264)))
1571 pcr->remap_addr = ioremap(base, len);
1572 if (!pcr->remap_addr) {
1577 pcr->rtsx_resv_buf = dma_alloc_coherent(&(pcidev->dev),
1578 RTSX_RESV_BUF_LEN, &(pcr->rtsx_resv_buf_addr),
1580 if (pcr->rtsx_resv_buf == NULL) {
1584 pcr->host_cmds_ptr = pcr->rtsx_resv_buf;
1585 pcr->host_cmds_addr = pcr->rtsx_resv_buf_addr;
1586 pcr->host_sg_tbl_ptr = pcr->rtsx_resv_buf + HOST_CMDS_BUF_LEN;
1587 pcr->host_sg_tbl_addr = pcr->rtsx_resv_buf_addr + HOST_CMDS_BUF_LEN;
1588 pcr->card_inserted = 0;
1589 pcr->card_removed = 0;
1590 INIT_DELAYED_WORK(&pcr->carddet_work, rtsx_pci_card_detect);
1592 pcr->msi_en = msi_en;
1593 if (pcr->msi_en) {
1596 pcr->msi_en = false;
1599 ret = rtsx_pci_acquire_irq(pcr);
1604 synchronize_irq(pcr->irq);
1606 ret = rtsx_pci_init_chip(pcr);
1616 ret = mfd_add_devices(&pcidev->dev, pcr->id, rtsx_pcr_cells,
1627 kfree(pcr->slots);
1629 free_irq(pcr->irq, (void *)pcr);
1631 if (pcr->msi_en)
1632 pci_disable_msi(pcr->pci);
1633 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1634 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1636 iounmap(pcr->remap_addr);
1639 idr_remove(&rtsx_pci_idr, pcr->id);
1644 kfree(pcr);
1656 struct rtsx_pcr *pcr = handle->pcr;
1658 pcr->remove_pci = true;
1663 /* Disable interrupts at the pcr level */
1664 spin_lock_irq(&pcr->lock);
1665 rtsx_pci_writel(pcr, RTSX_BIER, 0);
1666 pcr->bier = 0;
1667 spin_unlock_irq(&pcr->lock);
1669 cancel_delayed_work_sync(&pcr->carddet_work);
1673 dma_free_coherent(&(pcr->pci->dev), RTSX_RESV_BUF_LEN,
1674 pcr->rtsx_resv_buf, pcr->rtsx_resv_buf_addr);
1675 free_irq(pcr->irq, (void *)pcr);
1676 if (pcr->msi_en)
1677 pci_disable_msi(pcr->pci);
1678 iounmap(pcr->remap_addr);
1684 idr_remove(&rtsx_pci_idr, pcr->id);
1687 kfree(pcr->slots);
1688 kfree(pcr);
1700 struct rtsx_pcr *pcr = handle->pcr;
1704 cancel_delayed_work_sync(&pcr->carddet_work);
1706 mutex_lock(&pcr->pcr_mutex);
1708 rtsx_pci_power_off(pcr, HOST_ENTER_S3, false);
1710 mutex_unlock(&pcr->pcr_mutex);
1718 struct rtsx_pcr *pcr = handle->pcr;
1723 mutex_lock(&pcr->pcr_mutex);
1725 ret = rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1729 ret = rtsx_pci_init_hw(pcr);
1734 mutex_unlock(&pcr->pcr_mutex);
1740 static void rtsx_enable_aspm(struct rtsx_pcr *pcr)
1742 if (pcr->ops->set_aspm)
1743 pcr->ops->set_aspm(pcr, true);
1745 rtsx_comm_set_aspm(pcr, true);
1748 static void rtsx_comm_pm_power_saving(struct rtsx_pcr *pcr)
1750 struct rtsx_cr_option *option = &pcr->option;
1755 if (rtsx_check_dev_flag(pcr, L1_SNOOZE_TEST_EN))
1758 rtsx_set_ltr_latency(pcr, latency);
1761 if (rtsx_check_dev_flag(pcr, LTR_L1SS_PWR_GATE_EN))
1762 rtsx_set_l1off_sub_cfg_d0(pcr, 0);
1764 rtsx_enable_aspm(pcr);
1767 static void rtsx_pm_power_saving(struct rtsx_pcr *pcr)
1769 rtsx_comm_pm_power_saving(pcr);
1775 struct rtsx_pcr *pcr = handle->pcr;
1779 rtsx_pci_power_off(pcr, HOST_ENTER_S1, false);
1782 free_irq(pcr->irq, (void *)pcr);
1783 if (pcr->msi_en)
1784 pci_disable_msi(pcr->pci);
1791 struct rtsx_pcr *pcr = handle->pcr;
1795 mutex_lock(&pcr->pcr_mutex);
1797 pcr->state = PDEV_STAT_IDLE;
1799 if (pcr->ops->disable_auto_blink)
1800 pcr->ops->disable_auto_blink(pcr);
1801 if (pcr->ops->turn_off_led)
1802 pcr->ops->turn_off_led(pcr);
1804 rtsx_pm_power_saving(pcr);
1806 mutex_unlock(&pcr->pcr_mutex);
1808 if (pcr->rtd3_en)
1818 struct rtsx_pcr *pcr = handle->pcr;
1822 cancel_delayed_work_sync(&pcr->carddet_work);
1824 mutex_lock(&pcr->pcr_mutex);
1825 rtsx_pci_power_off(pcr, HOST_ENTER_S3, true);
1827 mutex_unlock(&pcr->pcr_mutex);
1836 struct rtsx_pcr *pcr = handle->pcr;
1840 mutex_lock(&pcr->pcr_mutex);
1842 rtsx_pci_write_register(pcr, HOST_SLEEP_STATE, 0x03, 0x00);
1844 rtsx_pci_init_hw(pcr);
1846 if (pcr->slots[RTSX_SD_CARD].p_dev != NULL) {
1847 pcr->slots[RTSX_SD_CARD].card_event(
1848 pcr->slots[RTSX_SD_CARD].p_dev);
1851 mutex_unlock(&pcr->pcr_mutex);