Lines Matching refs:pcr
19 static u8 rts5260_get_ic_version(struct rtsx_pcr *pcr)
23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
27 static void rts5260_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
45 drive_sel = pcr->sd30_drive_sel_3v3;
48 drive_sel = pcr->sd30_drive_sel_1v8;
51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL,
54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL,
57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL,
61 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
63 struct pci_dev *pdev = pcr->pci;
67 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
70 pcr_dbg(pcr, "skip fetch vendor setting\n");
74 pcr->aspm_en = rtsx_reg_to_aspm(reg);
75 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
76 pcr->card_drive_sel &= 0x3F;
77 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
80 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
82 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
83 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
85 pcr->flags |= PCR_REVERSE_SOCKET;
88 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr)
90 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
94 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr)
96 return rtsx_pci_write_register(pcr, OLT_LED_CTL,
100 static int rts5260_turn_on_led(struct rtsx_pcr *pcr)
102 return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
106 static int rts5260_turn_off_led(struct rtsx_pcr *pcr)
108 return rtsx_pci_write_register(pcr, RTS5260_REG_GPIO_CTL0,
164 static int sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr)
166 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK
168 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
169 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF,
171 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0);
176 static int rts5260_card_power_on(struct rtsx_pcr *pcr, int card)
178 struct rtsx_cr_option *option = &pcr->option;
181 rtsx_pci_enable_ocp(pcr);
184 rtsx_pci_write_register(pcr, LDO_CONFIG2, DV331812_VDD1, DV331812_VDD1);
185 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
188 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_POW_SDVDD1_MASK,
191 rtsx_pci_write_register(pcr, LDO_CONFIG2,
195 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 ||
196 pcr->extra_caps & EXTRA_CAPS_SD_SDR104)
197 sd_set_sample_push_timing_sd30(pcr);
200 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF,
203 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL,
205 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0);
206 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR,
210 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0);
211 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG,
215 rtsx_pci_write_register(pcr, REG_PRE_RW_MODE, EN_INFINITE_MODE, 0);
220 static int rts5260_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
224 rtsx_pci_write_register(pcr, LDO_CONFIG2,
226 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
228 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0);
231 rtsx_pci_write_register(pcr, LDO_CONFIG2,
233 rtsx_pci_write_register(pcr, LDO_DV18_CFG,
235 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8,
243 rts5260_fill_driving(pcr, voltage);
248 static void rts5260_stop_cmd(struct rtsx_pcr *pcr)
250 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD);
251 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA);
252 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0,
255 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH);
258 static void rts5260_card_before_power_off(struct rtsx_pcr *pcr)
260 rts5260_stop_cmd(pcr);
261 rts5260_switch_output_voltage(pcr, OUTPUT_3V3);
265 static int rts5260_card_power_off(struct rtsx_pcr *pcr, int card)
269 rts5260_card_before_power_off(pcr);
270 err = rtsx_pci_write_register(pcr, LDO_VCC_CFG1,
272 err = rtsx_pci_write_register(pcr, LDO_CONFIG2,
274 if (pcr->option.ocp_en)
275 rtsx_pci_disable_ocp(pcr);
280 static void rts5260_init_ocp(struct rtsx_pcr *pcr)
282 struct rtsx_cr_option *option = &pcr->option;
288 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
292 rtsx_pci_write_register(pcr, RTS5260_DV331812_CFG,
297 val = pcr->hw_param.ocp_glitch;
298 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val);
299 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
305 rtsx_pci_enable_ocp(pcr);
307 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
313 static void rts5260_enable_ocp(struct rtsx_pcr *pcr)
318 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val);
322 static void rts5260_disable_ocp(struct rtsx_pcr *pcr)
327 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
332 static int rts5260_get_ocpstat(struct rtsx_pcr *pcr, u8 *val)
334 return rtsx_pci_read_register(pcr, REG_OCPSTAT, val);
337 static int rts5260_get_ocpstat2(struct rtsx_pcr *pcr, u8 *val)
339 return rtsx_pci_read_register(pcr, REG_DV3318_OCPSTAT, val);
342 static void rts5260_clear_ocpstat(struct rtsx_pcr *pcr)
350 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val);
351 rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
355 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0);
356 rtsx_pci_write_register(pcr, REG_DV3318_OCPCTL,
360 static void rts5260_process_ocp(struct rtsx_pcr *pcr)
362 if (!pcr->option.ocp_en)
365 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat);
366 rts5260_get_ocpstat2(pcr, &pcr->ocp_stat2);
368 if ((pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) ||
369 (pcr->ocp_stat2 & (DV3318_OCP_NOW | DV3318_OCP_EVER))) {
370 rtsx_pci_card_power_off(pcr, RTSX_SD_CARD);
371 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0);
372 rtsx_pci_clear_ocpstat(pcr);
373 pcr->ocp_stat = 0;
374 pcr->ocp_stat2 = 0;
379 static int rts5260_init_hw(struct rtsx_pcr *pcr)
383 rtsx_pci_init_cmd(pcr);
385 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG1,
388 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00);
389 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CLK_FORCE_CTL,
391 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWD_SUSPEND_EN, 0xFF, 0xFF);
392 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
394 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, REG_VREF,
396 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RBCTL,
399 if (pcr->flags & PCR_REVERSE_SOCKET)
400 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
402 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
404 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG,
407 err = rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
411 rtsx_pci_init_ocp(pcr);
416 static void rts5260_pwr_saving_setting(struct rtsx_pcr *pcr)
420 lss_l1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN)
421 | rtsx_check_dev_flag(pcr, PM_L1_1_EN);
422 lss_l1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN)
423 | rtsx_check_dev_flag(pcr, PM_L1_2_EN);
425 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0);
427 pcr_dbg(pcr, "Set parameters for L1.2.");
428 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
430 rtsx_pci_write_register(pcr, RTS5260_DVCC_CTRL,
436 rtsx_pci_write_register(pcr, PWR_FE_CTL,
439 pcr_dbg(pcr, "Set parameters for L1.1.");
440 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
442 rtsx_pci_write_register(pcr, PWR_FE_CTL,
445 pcr_dbg(pcr, "Set parameters for L1.");
446 rtsx_pci_write_register(pcr, PWR_GLOBAL_CTRL,
448 rtsx_pci_write_register(pcr, PWR_FE_CTL,
452 rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_DPHY_RET_VALUE,
454 rtsx_pci_write_register(pcr, CFG_L1_0_PCIE_MAC_RET_VALUE,
456 rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD30_RET_VALUE,
458 rtsx_pci_write_register(pcr, CFG_L1_0_CRC_SD40_RET_VALUE,
460 rtsx_pci_write_register(pcr, CFG_L1_0_SYS_RET_VALUE,
463 rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_0,
465 rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_1,
467 rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_2,
469 rtsx_pci_write_register(pcr, CFG_PCIE_APHY_OFF_3,
472 rtsx_pci_write_register(pcr, PWC_CDR, 0xFF, PWC_CDR_DEFAULT);
474 rtsx_pci_write_register(pcr, CFG_LP_FPWM_VALUE,
477 rtsx_pci_write_register(pcr, CFG_L1_0_CRC_MISC_RET_VALUE,
481 static void rts5260_init_from_cfg(struct rtsx_pcr *pcr)
483 struct rtsx_cr_option *option = &pcr->option;
485 rts5260_pwr_saving_setting(pcr);
489 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
493 static int rts5260_extra_init_hw(struct rtsx_pcr *pcr)
495 struct rtsx_cr_option *option = &pcr->option;
498 rtsx_pci_write_register(pcr, 0xFC03, 0x7F, 0x07);
499 rtsx_pci_write_register(pcr, SSC_DIV_N_0, 0xFF, 0x5D);
501 rts5260_init_from_cfg(pcr);
504 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4,
507 rtsx_pci_write_register(pcr, LDO_VCC_CFG0,
510 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL);
512 rts5260_init_hw(pcr);
519 rtsx_pci_write_register(pcr, PETXCFG,
522 rtsx_pci_write_register(pcr, PETXCFG,
525 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00);
530 static void rts5260_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
532 struct rtsx_cr_option *option = &pcr->option;
533 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR);
538 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
539 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
552 if (rtsx_check_dev_flag(pcr,
560 rtsx_set_l1off_sub(pcr, val);
583 void rts5260_init_params(struct rtsx_pcr *pcr)
585 struct rtsx_cr_option *option = &pcr->option;
586 struct rtsx_hw_param *hw_param = &pcr->hw_param;
588 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
589 pcr->num_slots = 2;
591 pcr->flags = 0;
592 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
593 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
594 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
595 pcr->aspm_en = ASPM_L1_EN;
596 pcr->aspm_mode = ASPM_MODE_REG;
597 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11);
598 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5);
600 pcr->ic_version = rts5260_get_ic_version(pcr);
601 pcr->sd_pull_ctl_enable_tbl = rts5260_sd_pull_ctl_enable_tbl;
602 pcr->sd_pull_ctl_disable_tbl = rts5260_sd_pull_ctl_disable_tbl;
603 pcr->ms_pull_ctl_enable_tbl = rts5260_ms_pull_ctl_enable_tbl;
604 pcr->ms_pull_ctl_disable_tbl = rts5260_ms_pull_ctl_disable_tbl;
606 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3;
608 pcr->ops = &rts5260_pcr_ops;