misc/cardreader/rts5229.c

16 static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr)
20 	rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
24 static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr)
26 	struct pci_dev *pdev = pcr->pci;
30 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
35 	pcr->aspm_en = rtsx_reg_to_aspm(reg);
36 	pcr->sd30_drive_sel_1v8 =
38 	pcr->card_drive_sel &= 0x3F;
39 	pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
42 	pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
43 	pcr->sd30_drive_sel_3v3 =
47 static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
49 	rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
52 static int rts5229_extra_init_hw(struct rtsx_pcr *pcr)
54 	rtsx_pci_init_cmd(pcr);
57 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
59 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
61 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08);
63 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
64 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
66 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
68 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
69 			0xFF, pcr->sd30_drive_sel_3v3);
71 	return rtsx_pci_send_cmd(pcr, 100);
74 static int rts5229_optimize_phy(struct rtsx_pcr *pcr)
77 	return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
80 static int rts5229_turn_on_led(struct rtsx_pcr *pcr)
82 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
85 static int rts5229_turn_off_led(struct rtsx_pcr *pcr)
87 	return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
90 static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr)
92 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
95 static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr)
97 	return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
100 static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card)
104 	rtsx_pci_init_cmd(pcr);
105 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
107 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
109 	err = rtsx_pci_send_cmd(pcr, 100);
116 	rtsx_pci_init_cmd(pcr);
117 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
119 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
121 	return rtsx_pci_send_cmd(pcr, 100);
124 static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card)
126 	rtsx_pci_init_cmd(pcr);
127 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
130 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
132 	return rtsx_pci_send_cmd(pcr, 100);
135 static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
140 		err = rtsx_pci_write_register(pcr,
141 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
144 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
148 		err = rtsx_pci_write_register(pcr,
149 				SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
152 		err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24);
238 void rts5229_init_params(struct rtsx_pcr *pcr)
240 	pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
241 	pcr->num_slots = 2;
242 	pcr->ops = &rts5229_pcr_ops;
244 	pcr->flags = 0;
245 	pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
246 	pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
247 	pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
248 	pcr->aspm_en = ASPM_L1_EN;
249 	pcr->aspm_mode = ASPM_MODE_CFG;
250 	pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
251 	pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6);
253 	pcr->ic_version = rts5229_get_ic_version(pcr);
254 	if (pcr->ic_version == IC_VER_C) {
255 		pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2;
256 		pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2;
258 		pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1;
259 		pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1;
261 	pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl;
262 	pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl;