Lines Matching refs:pcr
17 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
21 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
25 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
43 drive_sel = pcr->sd30_drive_sel_3v3;
46 drive_sel = pcr->sd30_drive_sel_1v8;
49 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
51 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
57 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
59 struct pci_dev *pdev = pcr->pci;
63 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
68 pcr->aspm_en = rtsx_reg_to_aspm(reg);
69 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
70 pcr->card_drive_sel &= 0x3F;
71 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
74 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
75 if (CHK_PCI_PID(pcr, 0x522A))
76 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
78 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
79 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
81 pcr->flags |= PCR_REVERSE_SOCKET;
84 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
86 struct rtsx_cr_option *option = &pcr->option;
88 if (CHK_PCI_PID(pcr, 0x522A)) {
89 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
91 rtsx_pci_disable_oobs_polling(pcr);
93 rtsx_pci_enable_oobs_polling(pcr);
98 rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
102 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
105 struct rtsx_cr_option *option = &pcr->option;
107 rts5227_init_from_cfg(pcr);
108 rtsx_pci_init_cmd(pcr);
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
118 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
120 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
122 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
126 rts5227_fill_driving(pcr, OUTPUT_3V3);
128 if (pcr->flags & PCR_REVERSE_SOCKET)
129 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
131 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
133 if (CHK_PCI_PID(pcr, 0x522A))
134 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
137 if (pcr->rtd3_en) {
138 if (CHK_PCI_PID(pcr, 0x522A)) {
139 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
140 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
142 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
143 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
146 if (CHK_PCI_PID(pcr, 0x522A)) {
147 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
150 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
151 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
156 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
159 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
162 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
164 return rtsx_pci_send_cmd(pcr, 100);
167 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
171 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
176 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
179 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
181 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
184 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
186 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
189 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
191 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
194 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
196 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
199 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
203 if (pcr->option.ocp_en)
204 rtsx_pci_enable_ocp(pcr);
206 rtsx_pci_init_cmd(pcr);
207 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
210 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
213 err = rtsx_pci_send_cmd(pcr, 100);
219 rtsx_pci_init_cmd(pcr);
220 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
223 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
226 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
228 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
230 return rtsx_pci_send_cmd(pcr, 100);
233 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
235 if (pcr->option.ocp_en)
236 rtsx_pci_disable_ocp(pcr);
238 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
240 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
245 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
250 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
254 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
257 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
265 rtsx_pci_init_cmd(pcr);
266 rts5227_fill_driving(pcr, voltage);
267 return rtsx_pci_send_cmd(pcr, 100);
331 void rts5227_init_params(struct rtsx_pcr *pcr)
333 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
334 pcr->num_slots = 2;
335 pcr->ops = &rts5227_pcr_ops;
337 pcr->flags = 0;
338 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
339 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
340 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
341 pcr->aspm_en = ASPM_L1_EN;
342 pcr->aspm_mode = ASPM_MODE_CFG;
343 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
344 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
346 pcr->ic_version = rts5227_get_ic_version(pcr);
347 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
348 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
349 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
350 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
352 pcr->reg_pm_ctrl3 = PM_CTRL3;
355 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
359 err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
364 if (is_version(pcr, 0x522A, IC_VER_A)) {
365 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
370 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
371 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
372 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
373 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
379 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
381 rts5227_extra_init_hw(pcr);
384 if (!pcr->card_exist)
385 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
388 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
390 rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
391 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
392 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
397 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
402 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
406 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
409 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
417 rtsx_pci_init_cmd(pcr);
418 rts5227_fill_driving(pcr, voltage);
419 return rtsx_pci_send_cmd(pcr, 100);
422 static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
425 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
426 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
427 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
430 rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
434 rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
436 rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
437 rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
440 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
444 static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
446 struct rtsx_cr_option *option = &pcr->option;
450 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
451 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
463 rtsx_set_l1off_sub(pcr, val);
485 void rts522a_init_params(struct rtsx_pcr *pcr)
487 struct rtsx_cr_option *option = &pcr->option;
489 rts5227_init_params(pcr);
490 pcr->ops = &rts522a_pcr_ops;
491 pcr->aspm_mode = ASPM_MODE_REG;
492 pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
493 pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
506 pcr->option.ocp_en = 1;
507 if (pcr->option.ocp_en)
508 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
509 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
510 pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;