Lines Matching refs:U32
353 U32 Word32;
512 U32 MsgContext; /* 08h */
515 U32 PageAddress; /* 18h */
543 U32 MsgContext; /* 08h */
546 U32 IOCLogInfo; /* 10h */
637 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
656 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
666 U32 Reserved1; /* 04h */
675 U32 ISVolumeSettings; /* 48h */
676 U32 IMEVolumeSettings; /* 4Ch */
677 U32 IMVolumeSettings; /* 50h */
678 U32 Reserved3; /* 54h */
679 U32 Reserved4; /* 58h */
680 U32 Reserved5; /* 5Ch */
687 U32 Reserved8; /* 68h */
688 U32 Reserved9; /* 6Ch */
730 U32 Reserved3; /* 10h */
731 U32 Reserved4; /* 14h */
745 U32 ProductSpecificInfo;/* 04h */
754 U32 Pinout; /* 00h */
759 U32 Reserved2; /* 18h */
795 U32 Reserved1; /* 04h */
796 U32 Reserved2; /* 08h */
797 U32 Flags; /* 0Ch */
815 U32 ProductSpecificInfo;/* 04h */
825 U32 ProductSpecificInfo;/* 04h */
835 U32 ProductSpecificInfo;/* 04h */
859 U32 Flags; /* 04h */
891 U32 Flags; /* 04h */
892 U32 BiosVersion; /* 08h */
894 U32 Reserved1; /* 1Ch */
940 U32 Reserved1; /* 04h */
955 U32 TotalNVStore; /* 04h */
956 U32 FreeNVStore; /* 08h */
961 U32 ClassCode; /* 14h */
973 U32 Flags; /* 04h */
974 U32 CoalescingTimeout; /* 08h */
1032 U32 CapabilitiesFlags; /* 04h */
1140 U32 Reserved1; /* 04h */
1153 U32 CapabilitiesFlags; /* 04h */
1165 U32 Reserved5; /* 14h */
1166 U32 SupportedStripeSizeMapIS; /* 18h */
1167 U32 SupportedStripeSizeMapIME; /* 1Ch */
1168 U32 Reserved6; /* 20h */
1176 U32 IRNvsramVersion; /* 30h */
1177 U32 Reserved11; /* 34h */
1178 U32 Reserved12; /* 38h */
1204 U32 BiosOptions; /* 04h */
1205 U32 IOCSettings; /* 08h */
1206 U32 Reserved1; /* 0Ch */
1207 U32 DeviceSettings; /* 10h */
1273 U32 Reserved1; /* 00h */
1274 U32 Reserved2; /* 04h */
1275 U32 Reserved3; /* 08h */
1276 U32 Reserved4; /* 0Ch */
1277 U32 Reserved5; /* 10h */
1278 U32 Reserved6; /* 14h */
1279 U32 Reserved7; /* 18h */
1280 U32 Reserved8; /* 1Ch */
1281 U32 Reserved9; /* 20h */
1282 U32 Reserved10; /* 24h */
1283 U32 Reserved11; /* 28h */
1284 U32 Reserved12; /* 2Ch */
1285 U32 Reserved13; /* 30h */
1286 U32 Reserved14; /* 34h */
1287 U32 Reserved15; /* 38h */
1288 U32 Reserved16; /* 3Ch */
1289 U32 Reserved17; /* 40h */
1298 U32 Reserved2; /* 04h */
1299 U32 Reserved3; /* 08h */
1300 U32 Reserved4; /* 0Ch */
1302 U32 Reserved5; /* 18h */
1303 U32 Reserved6; /* 1Ch */
1304 U32 Reserved7; /* 20h */
1305 U32 Reserved8; /* 24h */
1306 U32 Reserved9; /* 28h */
1307 U32 Reserved10; /* 2Ch */
1308 U32 Reserved11; /* 30h */
1309 U32 Reserved12; /* 34h */
1310 U32 Reserved13; /* 38h */
1311 U32 Reserved14; /* 3Ch */
1312 U32 Reserved15; /* 40h */
1320 U32 Reserved1; /* 04h */
1321 U32 Reserved2; /* 08h */
1322 U32 Reserved3; /* 0Ch */
1324 U32 Reserved4; /* 18h */
1325 U32 Reserved5; /* 1Ch */
1326 U32 Reserved6; /* 20h */
1327 U32 Reserved7; /* 24h */
1328 U32 Reserved8; /* 28h */
1329 U32 Reserved9; /* 2Ch */
1330 U32 Reserved10; /* 30h */
1331 U32 Reserved11; /* 34h */
1332 U32 Reserved12; /* 38h */
1333 U32 Reserved13; /* 3Ch */
1334 U32 Reserved14; /* 40h */
1343 U32 Reserved2; /* 04h */
1344 U32 Reserved3; /* 08h */
1345 U32 Reserved4; /* 0Ch */
1347 U32 Reserved5; /* 18h */
1348 U32 Reserved6; /* 1Ch */
1349 U32 Reserved7; /* 20h */
1350 U32 Reserved8; /* 24h */
1351 U32 Reserved9; /* 28h */
1352 U32 Reserved10; /* 2Ch */
1353 U32 Reserved11; /* 30h */
1354 U32 Reserved12; /* 34h */
1355 U32 Reserved13; /* 38h */
1356 U32 Reserved14; /* 3Ch */
1357 U32 Reserved15; /* 40h */
1363 U32 Reserved1; /* 08h */
1364 U32 Reserved2; /* 0Ch */
1366 U32 Reserved3; /* 18h */
1367 U32 Reserved4; /* 1Ch */
1368 U32 Reserved5; /* 20h */
1369 U32 Reserved6; /* 24h */
1370 U32 Reserved7; /* 28h */
1371 U32 Reserved8; /* 2Ch */
1372 U32 Reserved9; /* 30h */
1373 U32 Reserved10; /* 34h */
1374 U32 Reserved11; /* 38h */
1375 U32 Reserved12; /* 3Ch */
1376 U32 Reserved13; /* 40h */
1382 U32 Reserved1; /* 08h */
1383 U32 Reserved2; /* 0Ch */
1385 U32 Reserved3; /* 18h */
1386 U32 Reserved4; /* 1Ch */
1387 U32 Reserved5; /* 20h */
1388 U32 Reserved6; /* 24h */
1389 U32 Reserved7; /* 28h */
1390 U32 Reserved8; /* 2Ch */
1391 U32 Reserved9; /* 30h */
1392 U32 Reserved10; /* 34h */
1393 U32 Reserved11; /* 38h */
1394 U32 Reserved12; /* 3Ch */
1395 U32 Reserved13; /* 40h */
1401 U32 Reserved1; /* 08h */
1402 U32 Reserved2; /* 0Ch */
1406 U32 Reserved4; /* 1Ch */
1407 U32 Reserved5; /* 20h */
1408 U32 Reserved6; /* 24h */
1409 U32 Reserved7; /* 28h */
1410 U32 Reserved8; /* 2Ch */
1411 U32 Reserved9; /* 30h */
1412 U32 Reserved10; /* 34h */
1413 U32 Reserved11; /* 38h */
1414 U32 Reserved12; /* 3Ch */
1415 U32 Reserved13; /* 40h */
1433 U32 Reserved1; /* 04h */
1434 U32 Reserved2; /* 08h */
1435 U32 Reserved3; /* 0Ch */
1436 U32 Reserved4; /* 10h */
1437 U32 Reserved5; /* 14h */
1438 U32 Reserved6; /* 18h */
1474 U32 Capabilities; /* 04h */
1475 U32 PhysicalInterface; /* 08h */
1523 U32 Configuration; /* 04h */
1524 U32 OnBusTimerValue; /* 08h */
1554 U32 PortFlags; /* 04h */
1555 U32 PortSettings; /* 08h */
1607 U32 NegotiatedParameters; /* 04h */
1608 U32 Information; /* 08h */
1639 U32 RequestedParameters; /* 04h */
1640 U32 Reserved; /* 08h */
1641 U32 Configuration; /* 0Ch */
1672 U32 DomainValidation; /* 04h */
1673 U32 ParityPipeSelect; /* 08h */
1674 U32 DataPipeSelect; /* 0Ch */
1733 U32 Flags; /* 04h */
1738 U32 PortIdentifier; /* 0Ch */
1741 U32 SupportedServiceClass; /* 20h */
1742 U32 SupportedSpeeds; /* 24h */
1743 U32 CurrentSpeed; /* 28h */
1744 U32 MaxFrameSize; /* 2Ch */
1747 U32 DiscoveredPortsCount; /* 40h */
1748 U32 MaxInitiators; /* 44h */
1822 U32 Flags; /* 04h */
1855 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1856 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1857 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1858 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1906 U32 Did;
1947 U32 PortFlags; /* 04h */
1948 U32 PortSettings; /* 08h */
1994 U32 Reserved; /* 04h */
2020 U32 Reserved; /* 04h */
2031 U32 BitVector[8]; /* 04h */
2041 U32 Reserved; /* 04h */
2044 U32 UnitType; /* 18h */
2045 U32 PhysicalPortNumber; /* 1Ch */
2046 U32 NumAttachedNodes; /* 20h */
2158 U32 HwConfig1; /* 08h */
2159 U32 HwConfig2; /* 0Ch */
2195 U32 PortIdentifier; /* 14h */
2315 U32 MaxLBA; /* 10h */
2316 U32 MaxLBAHigh; /* 14h */
2317 U32 StripeSize; /* 18h */
2318 U32 Reserved2; /* 1Ch */
2319 U32 Reserved3; /* 20h */
2350 U32 Reserved1; /* 48h */
2351 U32 Reserved2; /* 4Ch */
2427 U32 Reserved1; /* 0Ch */
2432 U32 MaxLBA; /* 68h */
2472 U32 Reserved1; /* 08h */
2489 U32 PacketPrePad; /* 08h */
2505 U32 MinPacketSize; /* 08h */
2506 U32 MaxPacketSize; /* 0Ch */
2507 U32 HardwareAddressLow; /* 10h */
2508 U32 HardwareAddressHigh; /* 14h */
2509 U32 MaxWireSpeedLow; /* 18h */
2510 U32 MaxWireSpeedHigh; /* 1Ch */
2511 U32 BucketsRemaining; /* 20h */
2512 U32 MaxReplySize; /* 24h */
2513 U32 NegWireSpeedLow; /* 28h */
2514 U32 NegWireSpeedHigh; /* 2Ch */
2551 U32 ControllerPhyDeviceInfo;/* 04h */
2554 U32 DiscoveryStatus; /* 0Ch */
2625 U32 ControllerPhyDeviceInfo; /* 04h */
2753 U32 Reserved1; /* 08h */
2754 U32 MaxInvalidDwordCount; /* 0Ch */
2755 U32 InvalidDwordCountTime; /* 10h */
2756 U32 MaxRunningDisparityErrorCount; /* 14h */
2757 U32 RunningDisparityErrorTime; /* 18h */
2758 U32 MaxLossDwordSynchCount; /* 1Ch */
2759 U32 LossDwordSynchCountTime; /* 20h */
2760 U32 MaxPhyResetProblemCount; /* 24h */
2761 U32 PhyResetProblemTime; /* 28h */
2779 U32 DiscoveryStatus; /* 14h */
2825 U32 PhyInfo; /* 14h */
2826 U32 AttachedDeviceInfo; /* 18h */
2834 U32 Reserved4; /* 24h */
2878 U32 DeviceInfo; /* 1Ch */
2925 U32 Reserved1; /* 08h */
2927 U32 Reserved2; /* 14h */
2942 U32 EnclosureMapping; /* 10h */
2970 U32 AttachedDeviceInfo; /* 18h */
2975 U32 PhyInfo; /* 20h */
3027 U32 Reserved1; /* 08h */
3028 U32 InvalidDwordCount; /* 0Ch */
3029 U32 RunningDisparityErrorCount; /* 10h */
3030 U32 LossDwordSynchCount; /* 14h */
3031 U32 PhyResetProblemCount; /* 18h */
3045 U32 Reserved1; /* 08h */
3055 U32 Reserved2; /* 20h */
3056 U32 Reserved3; /* 24h */
3090 U32 TimeStamp; /* 00h */
3091 U32 Reserved1; /* 04h */
3105 U32 Reserved1; /* 08h */
3106 U32 Reserved2; /* 0Ch */