memstick/host/rtsx_pci_ms.c

20 	struct rtsx_pcr		*pcr;
40 	rtsx_pci_write_register(host->pcr, CARD_STOP,
48 	struct rtsx_pcr *pcr = host->pcr;
53 	rtsx_pci_init_cmd(pcr);
55 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
57 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0);
58 	rtsx_pci_send_cmd(pcr, 100);
60 	ptr = rtsx_pci_get_cmd_data(pcr);
75 	struct rtsx_pcr *pcr = host->pcr;
78 	rtsx_pci_init_cmd(pcr);
79 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, MS_MOD_SEL);
80 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE,
82 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN,
84 	err = rtsx_pci_send_cmd(pcr, 100);
88 	err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_MS_CARD);
92 	err = rtsx_pci_card_power_on(pcr, RTSX_MS_CARD);
99 	err = rtsx_pci_write_register(pcr, CARD_OE,
109 	struct rtsx_pcr *pcr = host->pcr;
112 	rtsx_pci_init_cmd(pcr);
114 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
115 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
117 	err = rtsx_pci_send_cmd(pcr, 100);
121 	err = rtsx_pci_card_power_off(pcr, RTSX_MS_CARD);
125 	return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_MS_CARD);
131 	struct rtsx_pcr *pcr = host->pcr;
151 	rtsx_pci_init_cmd(pcr);
153 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
155 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_H,
157 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_SECTOR_CNT_L,
160 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
162 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0,
164 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(length >> 24));
165 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(length >> 16));
166 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(length >> 8));
167 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)length);
168 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL,
170 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
173 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
175 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
178 	rtsx_pci_send_cmd_no_wait(pcr);
180 	err = rtsx_pci_transfer_data(pcr, sg, 1, data_dir == READ, 10000);
186 	rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
202 	struct rtsx_pcr *pcr = host->pcr;
210 	rtsx_pci_init_cmd(pcr);
213 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
216 		rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
219 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
220 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
221 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
222 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
225 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
227 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
230 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
232 	err = rtsx_pci_send_cmd(pcr, 5000);
236 		rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
260 		u8 *ptr = rtsx_pci_get_cmd_data(pcr) + 1;
270 	struct rtsx_pcr *pcr = host->pcr;
279 	rtsx_pci_init_cmd(pcr);
281 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
282 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
283 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
284 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE,
287 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, MS_TRANSFER,
289 	rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, MS_TRANSFER,
292 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
294 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, PPBUF_BASE2 + cnt, 0, 0);
296 		rtsx_pci_add_cmd(pcr, READ_REG_CMD,
299 		rtsx_pci_add_cmd(pcr, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
301 	err = rtsx_pci_send_cmd(pcr, 5000);
305 		rtsx_pci_read_register(pcr, MS_TRANS_CFG, &val);
328 	ptr = rtsx_pci_get_cmd_data(pcr) + 1;
393 	struct rtsx_pcr *pcr = host->pcr;
397 	mutex_lock(&pcr->pcr_mutex);
399 	rtsx_pci_start_run(pcr);
401 	rtsx_pci_switch_clock(host->pcr, host->clock, host->ssc_depth,
403 	rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, MS_MOD_SEL);
404 	rtsx_pci_write_register(pcr, CARD_SHARE_MODE,
417 	mutex_unlock(&pcr->pcr_mutex);
426 	if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD))
436 	struct rtsx_pcr *pcr = host->pcr;
444 	err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_MS_CARD);
463 			err = rtsx_pci_write_register(pcr, MS_CFG, 0x58,
471 			err = rtsx_pci_write_register(pcr, MS_CFG,
479 		err = rtsx_pci_switch_clock(pcr, clock,
535 	struct rtsx_pcr *pcr;
542 	pcr = handle->pcr;
543 	if (!pcr)
554 	host->pcr = pcr;
558 	pcr->slots[RTSX_MS_CARD].p_dev = pdev;
559 	pcr->slots[RTSX_MS_CARD].card_event = rtsx_pci_ms_card_event;
580 	struct rtsx_pcr *pcr;
587 	pcr = host->pcr;
588 	pcr->slots[RTSX_MS_CARD].p_dev = NULL;
589 	pcr->slots[RTSX_MS_CARD].card_event = NULL;
600 		rtsx_pci_complete_unfinished_transfer(pcr);