50 	ldr	r1, [r0, #EMIF_SDRAM_CONFIG]
51 	str	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
53 	ldr	r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
54 	str	r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
56 	ldr	r1, [r0, #EMIF_SDRAM_TIMING_1]
57 	str     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
59 	ldr	r1, [r0, #EMIF_SDRAM_TIMING_2]
60 	str     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
62 	ldr	r1, [r0, #EMIF_SDRAM_TIMING_3]
63 	str     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
65 	ldr	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
66 	str     r1, [r2, #EMIF_PMCR_VAL_OFFSET]
68 	ldr	r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
69 	str     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
71 	ldr	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
72 	str     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
74 	ldr	r1, [r0, #EMIF_DDR_PHY_CTRL_1]
75 	str     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
77 	ldr	r1, [r0, #EMIF_COS_CONFIG]
78 	str     r1, [r2, #EMIF_COS_CONFIG_OFFSET]
80 	ldr	r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
81 	str     r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
83 	ldr	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
84 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
86 	ldr	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
87 	str     r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
89 	ldr	r1, [r0, #EMIF_OCP_CONFIG]
90 	str     r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
96 	ldr	r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
97 	str     r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
99 	ldr	r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
100 	str     r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
102 	ldr	r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
103 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
105 	ldr	r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
106 	str     r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
108 	ldr	r1, [r0, #EMIF_DLL_CALIB_CTRL]
109 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
111 	ldr	r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
112 	str     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
119 	ldr	r1, [r3, r5]
120 	str	r1, [r4, r5]
142 	ldr     r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
143 	str	r1, [r0, #EMIF_DDR_PHY_CTRL_1]
144 	str	r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
146 	ldr     r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
147 	str	r1, [r0, #EMIF_SDRAM_TIMING_1]
148 	str	r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
150 	ldr     r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
151 	str	r1, [r0, #EMIF_SDRAM_TIMING_2]
152 	str	r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
154 	ldr     r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
155 	str	r1, [r0, #EMIF_SDRAM_TIMING_3]
156 	str	r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
158 	ldr     r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
159 	str	r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
160 	str	r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
162 	ldr     r1, [r2, #EMIF_PMCR_VAL_OFFSET]
163 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
165 	ldr     r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
166 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
168 	ldr     r1, [r2, #EMIF_COS_CONFIG_OFFSET]
169 	str	r1, [r0, #EMIF_COS_CONFIG]
171 	ldr     r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
172 	str	r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
174 	ldr	r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
175 	str	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
177 	ldr     r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
178 	str	r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
180 	ldr     r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
181 	str	r1, [r0, #EMIF_OCP_CONFIG]
187 	ldr     r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
188 	str	r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
190 	ldr     r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
191 	str	r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
193 	ldr     r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
194 	str	r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
196 	ldr     r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
197 	str	r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
199 	ldr     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
200 	str	r1, [r0, #EMIF_DLL_CALIB_CTRL]
202 	ldr     r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
203 	str	r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
205 	ldr     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
206 	str	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
216 	ldr	r1, [r3, r5]
217 	str	r1, [r4, r5]
229 	ldr     r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
230 	str	r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
233 	ldr	r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
234 	and	r2, r1, #SDRAM_TYPE_MASK
236 	streq	r1, [r0, #EMIF_SDRAM_CONFIG]
273 2:	ldr     r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
274 	tst     r1, #RDWRLVLFULL_START
295 	ldr	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
296 	bic	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
297 	orr	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
298 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
323 	ldr	r1, [r2, #EMIF_PMCR_VAL_OFFSET]
324 	bic	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
325 	orr	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
326 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
327 	bic	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
328 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
331 1:	ldr     r1, [r0, #EMIF_STATUS]
332 	tst     r1, #EMIF_STATUS_READY
352 	ldr	r1, [r2, #EMIF_PMCR_VAL_OFFSET]
353 	bic	r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
354 	str	r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
357 1:	ldr     r1, [r0, #EMIF_STATUS]
358 	tst     r1, #EMIF_STATUS_READY

Indexes created Sat May 04 09:44:38 MDT 2024