drivers/memory/mtk-smi.c

19 #include <soc/mediatek/smi.h>
104 	MTK_SMI_GEN2,		/* gen2 smi common */
105 	MTK_SMI_GEN2_SUB_COMM,	/* gen2 smi sub common */
108 /* larbs: Require apb/smi clocks while gals is optional. */
109 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
114  * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
115  * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
117 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
153 	struct mtk_smi			smi;
440 	{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
441 	{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
442 	{.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
443 	{.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
444 	{.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
445 	{.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
446 	{.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
447 	{.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
448 	{.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
449 	{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
450 	{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
464 		dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
481 	smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
488 		/* smi common is the supplier, Make sure it is ready before */
497 			dev_err(dev, "Unable to link smi-common dev\n");
509 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
517 		smi->clks[i].id = clks[i];
518 	ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
523 		smi->clks[i].id = clks[i];
525 					 smi->clks + clk_nr_required);
526 	smi->clk_num = clk_nr_required + clk_nr_optional;
545 	ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
550 	larb->smi.dev = dev;
584 	ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
606 	clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
620 		.name = "mtk-smi-larb",
721 	{.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
722 	{.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
723 	{.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
724 	{.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
725 	{.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
726 	{.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
727 	{.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
728 	{.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
729 	{.compatible = "mediatek,mt8188-smi-common-vdo", .data = &mtk_smi_common_mt8188_vdo},
730 	{.compatible = "mediatek,mt8188-smi-common-vpp", .data = &mtk_smi_common_mt8188_vpp},
731 	{.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
732 	{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
733 	{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
734 	{.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
735 	{.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
762 	 * for mtk smi gen 1, we need to get the ao(always on) base to config
763 	 * m4u port, and we need to enable the aync clock for transform the smi
764 	 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
785 	/* link its smi-common if this is smi-sub-common */
845 		.name = "mtk-smi-common",