Lines Matching defs:hdw
18 #include "pvrusb2-hdw.h"
21 #include "pvrusb2-hdw-internal.h"
314 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
322 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
323 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
324 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
330 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
334 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
335 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
346 struct pvr2_hdw *hdw = cptr->hdw;
347 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
348 *vp = hdw->freqTable[hdw->freqProgSlot-1];
357 struct pvr2_hdw *hdw = cptr->hdw;
358 unsigned int slotId = hdw->freqProgSlot;
360 hdw->freqTable[slotId-1] = v;
364 if (hdw->freqSelector) {
365 if (hdw->freqSlotRadio == slotId) {
366 hdw->freqSlotRadio = 0;
369 if (hdw->freqSlotTelevision == slotId) {
370 hdw->freqSlotTelevision = 0;
379 *vp = cptr->hdw->freqProgSlot;
385 struct pvr2_hdw *hdw = cptr->hdw;
387 hdw->freqProgSlot = v;
394 struct pvr2_hdw *hdw = cptr->hdw;
395 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
402 struct pvr2_hdw *hdw = cptr->hdw;
405 freq = hdw->freqTable[slotId-1];
407 pvr2_hdw_set_cur_freq(hdw,freq);
409 if (hdw->freqSelector) {
410 hdw->freqSlotRadio = slotId;
412 hdw->freqSlotTelevision = slotId;
419 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
425 return cptr->hdw->freqDirty != 0;
430 cptr->hdw->freqDirty = 0;
435 pvr2_hdw_set_cur_freq(cptr->hdw,v);
441 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
442 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
452 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
453 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
458 if (cap->bounds.width > cptr->hdw->cropw_val) {
459 *left += cap->bounds.width - cptr->hdw->cropw_val;
466 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
467 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
477 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
478 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
483 if (cap->bounds.height > cptr->hdw->croph_val) {
484 *top += cap->bounds.height - cptr->hdw->croph_val;
491 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
494 stat = pvr2_hdw_check_cropcap(cptr->hdw);
499 cleft = cptr->hdw->cropl_val;
507 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
510 stat = pvr2_hdw_check_cropcap(cptr->hdw);
515 ctop = cptr->hdw->cropt_val;
523 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
524 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
534 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
535 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
545 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
546 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
556 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
557 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
567 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
568 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
578 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
579 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
589 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
590 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
600 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
601 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
611 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
612 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
622 struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
623 int stat = pvr2_hdw_check_cropcap(cptr->hdw);
634 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
645 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
655 *vp = cptr->hdw->input_val;
663 return ((1UL << v) & cptr->hdw->input_allowed_mask) != 0;
668 return pvr2_hdw_set_input(cptr->hdw,v);
673 return cptr->hdw->input_dirty != 0;
678 cptr->hdw->input_dirty = 0;
685 struct pvr2_hdw *hdw = cptr->hdw;
686 if (hdw->tuner_signal_stale) {
687 pvr2_hdw_status_poll(hdw);
689 fv = hdw->tuner_signal_info.rangehigh;
695 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
707 struct pvr2_hdw *hdw = cptr->hdw;
708 if (hdw->tuner_signal_stale) {
709 pvr2_hdw_status_poll(hdw);
711 fv = hdw->tuner_signal_info.rangelow;
717 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
728 return cptr->hdw->enc_stale != 0;
733 cptr->hdw->enc_stale = 0;
734 cptr->hdw->enc_unsafe_stale = 0;
747 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
757 struct pvr2_hdw *hdw = cptr->hdw;
766 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
767 hdw->state_encoder_run, &cs,
775 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
778 if (!ret) hdw->enc_unsafe_stale = !0;
781 hdw->enc_stale = !0;
790 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
812 *vp = cptr->hdw->state_pipeline_req;
818 *vp = cptr->hdw->master_state;
824 int result = pvr2_hdw_is_hsm(cptr->hdw);
833 *vp = pvr2_hdw_get_detected_std(cptr->hdw);
839 *vp = cptr->hdw->std_mask_avail;
845 struct pvr2_hdw *hdw = cptr->hdw;
847 ns = hdw->std_mask_avail;
849 if (ns == hdw->std_mask_avail) return 0;
850 hdw->std_mask_avail = ns;
851 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
877 *vp = cptr->hdw->std_mask_cur;
883 struct pvr2_hdw *hdw = cptr->hdw;
885 ns = hdw->std_mask_cur;
887 if (ns == hdw->std_mask_cur) return 0;
888 hdw->std_mask_cur = ns;
889 hdw->std_dirty = !0;
895 return cptr->hdw->std_dirty != 0;
900 cptr->hdw->std_dirty = 0;
905 struct pvr2_hdw *hdw = cptr->hdw;
906 pvr2_hdw_status_poll(hdw);
907 *vp = hdw->tuner_signal_info.signal;
915 struct pvr2_hdw *hdw = cptr->hdw;
916 pvr2_hdw_status_poll(hdw);
917 subchan = hdw->tuner_signal_info.rxsubchans;
962 {*vp = cptr->hdw->vname##_val; return 0;} \
964 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
966 {return cptr->hdw->vname##_dirty != 0;} \
968 {cptr->hdw->vname##_dirty = 0;}
1280 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1282 return hdw->usb_dev;
1286 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1288 return hdw->serial_number;
1292 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1294 return hdw->bus_info;
1298 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1300 return hdw->identifier;
1304 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1306 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1311 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1313 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1314 if (hdw->freqSelector) {
1316 hdw->freqSelector = 0;
1317 hdw->freqDirty = !0;
1319 if (hdw->freqValRadio != val) {
1320 hdw->freqValRadio = val;
1321 hdw->freqSlotRadio = 0;
1322 hdw->freqDirty = !0;
1325 if (!(hdw->freqSelector)) {
1327 hdw->freqSelector = 1;
1328 hdw->freqDirty = !0;
1330 if (hdw->freqValTelevision != val) {
1331 hdw->freqValTelevision = val;
1332 hdw->freqSlotTelevision = 0;
1333 hdw->freqDirty = !0;
1338 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1340 return hdw->unit_number;
1350 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1361 &hdw->usb_dev->dev);
1406 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1415 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1416 hdw->fw1_state = FW1_STATE_OK;
1422 hdw->fw1_state = FW1_STATE_FAILED; // default result
1426 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1427 hdw->hdw_desc->fx2_firmware.cnt,
1428 hdw->hdw_desc->fx2_firmware.lst);
1430 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1434 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1436 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1440 (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1441 if (hdw->hdw_desc->flag_fx2_16kb) {
1461 pvr2_hdw_cpureset_assert(hdw,1);
1469 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1476 pvr2_hdw_cpureset_assert(hdw,0);
1485 hdw->fw1_state = FW1_STATE_RELOAD;
1500 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1512 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1518 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1526 hdw->enc_cur_valid = 0;
1530 del_timer_sync(&hdw->encoder_run_timer);
1531 if (hdw->state_encoder_runok) {
1532 hdw->state_encoder_runok = 0;
1533 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1537 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1538 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1539 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1540 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1541 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1542 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1543 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1544 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1545 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1546 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1547 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1548 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1549 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1550 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1551 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1552 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1553 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1554 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1585 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1607 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1628 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1629 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1630 ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1638 if (hdw->hdw_desc->signal_routing_scheme ==
1642 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1656 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1664 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1665 v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1666 if (hdw->decoder_client_id) {
1672 if (!hdw->flag_decoder_missed) {
1675 hdw->flag_decoder_missed = !0;
1677 hdw->flag_decoder_missed);
1683 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1685 return hdw->master_state;
1689 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1691 if (!hdw->flag_tripped) return 0;
1692 hdw->flag_tripped = 0;
1699 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1702 LOCK_TAKE(hdw->big_lock); do {
1703 fl = pvr2_hdw_untrip_unlocked(hdw);
1704 } while (0); LOCK_GIVE(hdw->big_lock);
1705 if (fl) pvr2_hdw_state_sched(hdw);
1712 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1714 return hdw->state_pipeline_req != 0;
1718 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1721 LOCK_TAKE(hdw->big_lock);
1722 pvr2_hdw_untrip_unlocked(hdw);
1723 if (!enable_flag != !hdw->state_pipeline_req) {
1724 hdw->state_pipeline_req = enable_flag != 0;
1729 pvr2_hdw_state_sched(hdw);
1730 LOCK_GIVE(hdw->big_lock);
1731 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1733 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1735 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1742 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1745 LOCK_TAKE(hdw->big_lock);
1746 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1747 hdw->desired_stream_type = config;
1748 hdw->state_pipeline_config = 0;
1750 hdw->state_pipeline_config);
1751 pvr2_hdw_state_sched(hdw);
1753 LOCK_GIVE(hdw->big_lock);
1755 return pvr2_hdw_wait(hdw,0);
1759 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1761 int unit_number = hdw->unit_number;
1767 hdw->tuner_type = tp;
1768 hdw->tuner_updated = !0;
1773 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1775 int unit_number = hdw->unit_number;
1785 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1787 int unit_number = hdw->unit_number;
1796 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1803 LOCK_TAKE(hdw->ctl_lock); do {
1804 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1805 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1806 hdw->cmd_buffer,1,
1807 hdw->cmd_buffer,1);
1809 } while(0); LOCK_GIVE(hdw->ctl_lock);
1859 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1865 std1 = get_default_standard(hdw);
1866 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1868 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1873 hdw->std_mask_avail = hdw->std_mask_eeprom;
1875 std2 = (std1|std3) & ~hdw->std_mask_avail;
1881 hdw->std_mask_avail |= std2;
1884 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1891 hdw->std_mask_cur = std1;
1892 hdw->std_dirty = !0;
1900 hdw->std_mask_cur = std3;
1901 hdw->std_dirty = !0;
1910 hdw->std_mask_eeprom) &
1913 hdw->std_mask_eeprom)) continue;
1919 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1920 hdw->std_dirty = !0;
1943 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1955 if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1962 hdw->decoder_client_id);
1967 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1972 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1989 hdw->hdw_desc->description);
1995 hdw->hdw_desc->description);
2014 mid, fname, hdw->hdw_desc->description);
2022 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2028 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2035 mid, fname, hdw->hdw_desc->description);
2051 hdw->decoder_client_id = mid;
2060 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2067 cm = &hdw->hdw_desc->client_modules;
2072 ct = &hdw->hdw_desc->client_table;
2074 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2077 hdw->flag_modulefail = !0;
2078 pvr2_hdw_render_useless(hdw);
2083 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2089 if (hdw->hdw_desc->fx2_firmware.cnt) {
2092 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2100 reloadFl = !pvr2_hdw_check_firmware(hdw);
2107 if (pvr2_upload_firmware1(hdw) != 0) {
2114 hdw->fw1_state = FW1_STATE_OK;
2116 if (!pvr2_hdw_dev_ok(hdw)) return;
2118 hdw->force_dirty = !0;
2120 if (!hdw->hdw_desc->flag_no_powerup) {
2121 pvr2_hdw_cmd_powerup(hdw);
2122 if (!pvr2_hdw_dev_ok(hdw)) return;
2126 if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2127 pvr2_issue_simple_cmd(hdw,
2134 pvr2_i2c_core_init(hdw);
2135 if (!pvr2_hdw_dev_ok(hdw)) return;
2138 if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
2139 (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
2140 le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
2143 pvr2_issue_simple_cmd(hdw,
2148 pvr2_issue_simple_cmd(hdw,
2155 pvr2_hdw_load_modules(hdw);
2156 if (!pvr2_hdw_dev_ok(hdw)) return;
2158 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2161 cptr = hdw->controls + idx;
2167 pvr2_hdw_cx25840_vbi_hack(hdw);
2174 hdw->freqValTelevision = default_tv_freq;
2175 hdw->freqValRadio = default_radio_freq;
2181 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2182 ret = pvr2_hdw_get_eeprom_addr(hdw);
2183 if (!pvr2_hdw_dev_ok(hdw)) return;
2188 hdw->eeprom_addr = ret;
2189 pvr2_eeprom_analyze(hdw);
2190 if (!pvr2_hdw_dev_ok(hdw)) return;
2193 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2194 hdw->tuner_updated = !0;
2195 hdw->std_mask_eeprom = V4L2_STD_ALL;
2198 if (hdw->serial_number) {
2199 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2200 "sn-%lu", hdw->serial_number);
2201 } else if (hdw->unit_number >= 0) {
2202 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2204 hdw->unit_number + 'a');
2206 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2209 hdw->identifier[idx] = 0;
2211 pvr2_hdw_setup_std(hdw);
2213 if (!get_default_tuner_type(hdw)) {
2216 hdw->tuner_type);
2220 if (!pvr2_hdw_dev_ok(hdw)) return;
2222 if (hdw->hdw_desc->signal_routing_scheme ==
2226 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2229 pvr2_hdw_commit_setup(hdw);
2231 hdw->vid_stream = pvr2_stream_create();
2232 if (!pvr2_hdw_dev_ok(hdw)) return;
2234 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2235 if (hdw->vid_stream) {
2236 idx = get_default_error_tolerance(hdw);
2240 hdw->vid_stream,idx);
2242 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2246 if (!pvr2_hdw_dev_ok(hdw)) return;
2248 hdw->flag_init_ok = !0;
2250 pvr2_hdw_state_sched(hdw);
2257 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2259 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2261 pvr2_hdw_setup_low(hdw);
2263 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2264 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2265 if (pvr2_hdw_dev_ok(hdw)) {
2266 if (hdw->flag_init_ok) {
2272 if (hdw->fw1_state == FW1_STATE_RELOAD) {
2281 if (hdw->fw1_state == FW1_STATE_MISSING) {
2288 if (hdw->flag_modulefail) {
2304 hdw->fw1_state = FW1_STATE_UNKNOWN;
2305 pvr2_upload_firmware1(hdw);
2315 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2322 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2326 LOCK_TAKE(hdw->big_lock); do {
2327 if (hdw->flag_disconnected) {
2336 hdw->state_data = callback_data;
2337 hdw->state_func = callback_func;
2338 pvr2_hdw_setup(hdw);
2339 } while (0); LOCK_GIVE(hdw->big_lock);
2340 return hdw->flag_init_ok;
2350 struct pvr2_hdw *hdw = NULL;
2370 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2371 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2372 hdw,hdw_desc->description);
2386 if (!hdw) goto fail;
2388 timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2390 timer_setup(&hdw->decoder_stabilization_timer,
2393 timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2396 timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2398 hdw->master_state = PVR2_STATE_DEAD;
2400 init_waitqueue_head(&hdw->state_wait_data);
2402 hdw->tuner_signal_stale = !0;
2403 cx2341x_fill_defaults(&hdw->enc_ctl_state);
2414 hdw->input_avail_mask = m;
2415 hdw->input_allowed_mask = hdw->input_avail_mask;
2419 if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2420 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2421 } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2422 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2425 hdw->control_cnt = CTRLDEF_COUNT;
2426 hdw->control_cnt += MPEGDEF_COUNT;
2427 hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
2429 if (!hdw->controls) goto fail;
2430 hdw->hdw_desc = hdw_desc;
2431 hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2432 for (idx = 0; idx < hdw->control_cnt; idx++) {
2433 cptr = hdw->controls + idx;
2434 cptr->hdw = hdw;
2437 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2440 cptr = hdw->controls + idx;
2445 m = hdw->input_avail_mask;
2448 hdw->input_val = idx;
2453 hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2454 sizeof(*(hdw->mpeg_ctrl_info)),
2456 if (!hdw->mpeg_ctrl_info) goto fail;
2458 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2459 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2460 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2469 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2473 strscpy(hdw->mpeg_ctrl_info[idx].desc, qctrl.name,
2474 sizeof(hdw->mpeg_ctrl_info[idx].desc));
2489 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2505 hdw->std_mask_names[idx],
2506 sizeof(hdw->std_mask_names[idx])-1,
2508 hdw->std_mask_names[idx][cnt1] = 0;
2510 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2512 memcpy(&hdw->std_info_avail,cptr->info,
2513 sizeof(hdw->std_info_avail));
2514 cptr->info = &hdw->std_info_avail;
2515 hdw->std_info_avail.def.type_bitmask.bit_names =
2516 hdw->std_mask_ptrs;
2517 hdw->std_info_avail.def.type_bitmask.valid_bits =
2520 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2522 memcpy(&hdw->std_info_cur,cptr->info,
2523 sizeof(hdw->std_info_cur));
2524 cptr->info = &hdw->std_info_cur;
2525 hdw->std_info_cur.def.type_bitmask.bit_names =
2526 hdw->std_mask_ptrs;
2527 hdw->std_info_cur.def.type_bitmask.valid_bits =
2530 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2532 memcpy(&hdw->std_info_detect,cptr->info,
2533 sizeof(hdw->std_info_detect));
2534 cptr->info = &hdw->std_info_detect;
2535 hdw->std_info_detect.def.type_bitmask.bit_names =
2536 hdw->std_mask_ptrs;
2537 hdw->std_info_detect.def.type_bitmask.valid_bits =
2541 hdw->cropcap_stale = !0;
2542 hdw->eeprom_addr = -1;
2543 hdw->unit_number = -1;
2544 hdw->v4l_minor_number_video = -1;
2545 hdw->v4l_minor_number_vbi = -1;
2546 hdw->v4l_minor_number_radio = -1;
2547 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2548 if (!hdw->ctl_write_buffer) goto fail;
2549 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2550 if (!hdw->ctl_read_buffer) goto fail;
2551 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2552 if (!hdw->ctl_write_urb) goto fail;
2553 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2554 if (!hdw->ctl_read_urb) goto fail;
2556 if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2565 hdw->unit_number = idx;
2566 unit_pointers[idx] = hdw;
2572 INIT_WORK(&hdw->workpoll, pvr2_hdw_worker_poll);
2574 if (hdw->unit_number == -1)
2578 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2580 if (hdw->unit_number >= 0) {
2581 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2582 ('a' + hdw->unit_number));
2585 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2586 hdw->name[cnt1] = 0;
2589 hdw->unit_number,hdw->name);
2591 hdw->tuner_type = -1;
2592 hdw->flag_ok = !0;
2594 hdw->usb_intf = intf;
2595 hdw->usb_dev = usb_dev;
2597 usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2599 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2600 usb_set_interface(hdw->usb_dev,ifnum,0);
2602 mutex_init(&hdw->ctl_lock_mutex);
2603 mutex_init(&hdw->big_lock_mutex);
2605 return hdw;
2607 if (hdw) {
2608 timer_shutdown_sync(&hdw->quiescent_timer);
2609 timer_shutdown_sync(&hdw->decoder_stabilization_timer);
2610 timer_shutdown_sync(&hdw->encoder_run_timer);
2611 timer_shutdown_sync(&hdw->encoder_wait_timer);
2612 flush_work(&hdw->workpoll);
2613 v4l2_device_unregister(&hdw->v4l2_dev);
2614 usb_free_urb(hdw->ctl_read_urb);
2615 usb_free_urb(hdw->ctl_write_urb);
2616 kfree(hdw->ctl_read_buffer);
2617 kfree(hdw->ctl_write_buffer);
2618 kfree(hdw->controls);
2619 kfree(hdw->mpeg_ctrl_info);
2620 kfree(hdw);
2628 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2630 if (hdw->flag_disconnected) return;
2631 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2632 if (hdw->ctl_read_urb) {
2633 usb_kill_urb(hdw->ctl_read_urb);
2634 usb_free_urb(hdw->ctl_read_urb);
2635 hdw->ctl_read_urb = NULL;
2637 if (hdw->ctl_write_urb) {
2638 usb_kill_urb(hdw->ctl_write_urb);
2639 usb_free_urb(hdw->ctl_write_urb);
2640 hdw->ctl_write_urb = NULL;
2642 if (hdw->ctl_read_buffer) {
2643 kfree(hdw->ctl_read_buffer);
2644 hdw->ctl_read_buffer = NULL;
2646 if (hdw->ctl_write_buffer) {
2647 kfree(hdw->ctl_write_buffer);
2648 hdw->ctl_write_buffer = NULL;
2650 hdw->flag_disconnected = !0;
2654 v4l2_device_disconnect(&hdw->v4l2_dev);
2655 hdw->usb_dev = NULL;
2656 hdw->usb_intf = NULL;
2657 pvr2_hdw_render_useless(hdw);
2660 void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2662 vdev->v4l2_dev = &hdw->v4l2_dev;
2666 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2668 if (!hdw) return;
2669 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2670 flush_work(&hdw->workpoll);
2671 timer_shutdown_sync(&hdw->quiescent_timer);
2672 timer_shutdown_sync(&hdw->decoder_stabilization_timer);
2673 timer_shutdown_sync(&hdw->encoder_run_timer);
2674 timer_shutdown_sync(&hdw->encoder_wait_timer);
2675 if (hdw->fw_buffer) {
2676 kfree(hdw->fw_buffer);
2677 hdw->fw_buffer = NULL;
2679 if (hdw->vid_stream) {
2680 pvr2_stream_destroy(hdw->vid_stream);
2681 hdw->vid_stream = NULL;
2683 v4l2_device_unregister(&hdw->v4l2_dev);
2684 pvr2_hdw_disconnect(hdw);
2687 if ((hdw->unit_number >= 0) &&
2688 (hdw->unit_number < PVR_NUM) &&
2689 (unit_pointers[hdw->unit_number] == hdw)) {
2690 unit_pointers[hdw->unit_number] = NULL;
2694 kfree(hdw->controls);
2695 kfree(hdw->mpeg_ctrl_info);
2696 kfree(hdw);
2700 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2702 return (hdw && hdw->flag_ok);
2707 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2709 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2710 LOCK_TAKE(hdw->big_lock);
2711 pvr2_i2c_core_done(hdw);
2712 LOCK_TAKE(hdw->ctl_lock);
2713 pvr2_hdw_remove_usb_stuff(hdw);
2714 LOCK_GIVE(hdw->ctl_lock);
2715 LOCK_GIVE(hdw->big_lock);
2720 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2722 return hdw->control_cnt;
2727 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2730 if (idx >= hdw->control_cnt) return NULL;
2731 return hdw->controls + idx;
2736 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2744 for (idx = 0; idx < hdw->control_cnt; idx++) {
2745 cptr = hdw->controls + idx;
2754 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2761 for (idx = 0; idx < hdw->control_cnt; idx++) {
2762 cptr = hdw->controls + idx;
2772 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2781 for (idx = 0; idx < hdw->control_cnt; idx++) {
2782 cptr = hdw->controls + idx;
2806 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2817 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2821 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2822 if ((hdw)->lab##_dirty || (hdw)->force_dirty) { \
2823 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2826 static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2829 std = (v4l2_std_id)hdw->std_mask_avail;
2830 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2837 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2845 if (hdw->tuner_updated || hdw->force_dirty) {
2848 hdw->tuner_type);
2849 if (((int)(hdw->tuner_type)) >= 0) {
2852 setup.type = hdw->tuner_type;
2854 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2859 if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2861 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2862 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2866 vs = hdw->std_mask_cur;
2867 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2869 pvr2_hdw_cx25840_vbi_hack(hdw);
2871 hdw->tuner_signal_stale = !0;
2872 hdw->cropcap_stale = !0;
2875 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2876 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2877 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2878 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2879 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2880 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2881 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2882 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2883 PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2885 if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2888 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2890 vt.audmode = hdw->audiomode_val;
2891 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2894 if (hdw->freqDirty || hdw->force_dirty) {
2897 fv = pvr2_hdw_get_cur_freq(hdw);
2899 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2901 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2909 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2915 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2919 if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2924 format.format.width = hdw->res_hor_val;
2925 format.format.height = hdw->res_ver_val;
2929 v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2933 if (hdw->srate_dirty || hdw->force_dirty) {
2936 hdw->srate_val);
2937 switch (hdw->srate_val) {
2949 v4l2_device_call_all(&hdw->v4l2_dev, 0,
2956 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2961 (*fp)(hdw, sd);
2964 if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2965 pvr2_hdw_status_poll(hdw);
2973 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2978 int commit_flag = hdw->force_dirty;
2982 for (idx = 0; idx < hdw->control_cnt; idx++) {
2983 cptr = hdw->controls + idx;
3009 hdw->state_pipeline_config = 0;
3010 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3011 pvr2_hdw_state_sched(hdw);
3022 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3028 if (hdw->input_dirty && hdw->state_pathway_ok &&
3029 (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3031 hdw->pathway_state)) {
3033 hdw->state_pathway_ok = 0;
3034 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3036 if (!hdw->state_pathway_ok) {
3043 if (hdw->std_dirty) {
3046 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3055 if (nvres != hdw->res_ver_val) {
3056 hdw->res_ver_val = nvres;
3057 hdw->res_ver_dirty = !0;
3061 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3070 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3081 if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3082 hdw->cropw_val = hdw->res_hor_val;
3083 hdw->cropw_dirty = !0;
3084 } else if (hdw->cropw_dirty) {
3085 hdw->res_hor_dirty = !0; /* must rescale */
3086 hdw->res_hor_val = min(720, hdw->cropw_val);
3088 if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3089 hdw->croph_val = hdw->res_ver_val;
3090 hdw->croph_dirty = !0;
3091 } else if (hdw->croph_dirty) {
3092 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3093 hdw->res_ver_dirty = !0;
3094 hdw->res_ver_val = min(nvres, hdw->croph_val);
3102 (hdw->std_dirty ||
3103 hdw->enc_unsafe_stale ||
3104 hdw->srate_dirty ||
3105 hdw->res_ver_dirty ||
3106 hdw->res_hor_dirty ||
3107 hdw->cropw_dirty ||
3108 hdw->croph_dirty ||
3109 hdw->input_dirty ||
3110 (hdw->active_stream_type != hdw->desired_stream_type));
3111 if (disruptive_change && !hdw->state_pipeline_idle) {
3115 hdw->state_pipeline_pause = !0;
3119 if (hdw->srate_dirty) {
3131 c1.value = hdw->srate_val;
3132 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3135 if (hdw->active_stream_type != hdw->desired_stream_type) {
3137 hdw->active_stream_type = hdw->desired_stream_type;
3140 if (hdw->hdw_desc->signal_routing_scheme ==
3144 pvr2_hdw_gpio_get_out(hdw,&b);
3145 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3147 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3150 pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3155 pvr2_subdev_update(hdw);
3157 hdw->tuner_updated = 0;
3158 hdw->force_dirty = 0;
3159 for (idx = 0; idx < hdw->control_cnt; idx++) {
3160 cptr = hdw->controls + idx;
3165 if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3166 hdw->state_encoder_run) {
3170 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3173 hdw->state_pipeline_config = !0;
3177 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3182 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3185 LOCK_TAKE(hdw->big_lock);
3186 fl = pvr2_hdw_commit_setup(hdw);
3187 LOCK_GIVE(hdw->big_lock);
3189 return pvr2_hdw_wait(hdw,0);
3196 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3197 LOCK_TAKE(hdw->big_lock); do {
3198 fl = pvr2_hdw_state_eval(hdw);
3199 } while (0); LOCK_GIVE(hdw->big_lock);
3200 if (fl && hdw->state_func) {
3201 hdw->state_func(hdw->state_data);
3206 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3209 hdw->state_wait_data,
3210 (hdw->state_stale == 0) &&
3211 (!state || (hdw->master_state != state)));
3216 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3218 return hdw->name;
3222 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3224 return hdw->hdw_desc->description;
3228 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3230 return hdw->hdw_desc->shortname;
3234 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3237 LOCK_TAKE(hdw->ctl_lock); do {
3238 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3239 result = pvr2_send_request(hdw,
3240 hdw->cmd_buffer,1,
3241 hdw->cmd_buffer,1);
3243 result = (hdw->cmd_buffer[0] != 0);
3244 } while(0); LOCK_GIVE(hdw->ctl_lock);
3250 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3252 LOCK_TAKE(hdw->big_lock); do {
3253 pvr2_hdw_status_poll(hdw);
3254 } while (0); LOCK_GIVE(hdw->big_lock);
3258 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3260 if (!hdw->cropcap_stale) {
3263 pvr2_hdw_status_poll(hdw);
3264 if (hdw->cropcap_stale) {
3272 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3275 LOCK_TAKE(hdw->big_lock);
3276 stat = pvr2_hdw_check_cropcap(hdw);
3278 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3280 LOCK_GIVE(hdw->big_lock);
3286 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3288 LOCK_TAKE(hdw->big_lock);
3290 if (hdw->tuner_signal_stale) {
3291 pvr2_hdw_status_poll(hdw);
3293 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3295 LOCK_GIVE(hdw->big_lock);
3307 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3309 int nr = pvr2_hdw_get_unit_number(hdw);
3310 LOCK_TAKE(hdw->big_lock);
3313 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3315 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3316 pvr2_hdw_state_log_state(hdw);
3319 LOCK_GIVE(hdw->big_lock);
3326 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3345 hdw->eeprom_addr);
3346 addr = hdw->eeprom_addr;
3384 if ((ret = i2c_transfer(&hdw->i2c_adap,
3396 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3403 LOCK_TAKE(hdw->big_lock);
3405 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3410 kfree(hdw->fw_buffer);
3411 hdw->fw_buffer = NULL;
3412 hdw->fw_size = 0;
3413 if (hdw->fw_cpu_flag) {
3416 pvr2_hdw_cpureset_assert(hdw,0);
3421 hdw->fw_cpu_flag = (mode != 2);
3422 if (hdw->fw_cpu_flag) {
3423 hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3426 hdw->fw_size);
3427 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3428 if (!hdw->fw_buffer) {
3429 hdw->fw_size = 0;
3434 pvr2_hdw_cpureset_assert(hdw,1);
3441 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3442 for(address = 0; address < hdw->fw_size;
3444 ret = usb_control_msg(hdw->usb_dev,pipe,
3447 hdw->fw_buffer+address,
3457 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3458 if (!hdw->fw_buffer) {
3463 hdw->fw_size = EEPROM_SIZE;
3468 LOCK_GIVE(hdw->big_lock);
3473 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3475 return hdw->fw_buffer != NULL;
3479 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3483 LOCK_TAKE(hdw->big_lock);
3488 if (!hdw->fw_buffer) {
3493 if (offs >= hdw->fw_size) {
3501 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3503 memcpy(buf,hdw->fw_buffer+offs,cnt);
3510 LOCK_GIVE(hdw->big_lock);
3516 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3520 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3521 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3522 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3529 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3533 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3534 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3535 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3543 struct pvr2_hdw *hdw = urb->context;
3544 hdw->ctl_write_pend_flag = 0;
3545 if (hdw->ctl_read_pend_flag) return;
3546 complete(&hdw->ctl_done);
3552 struct pvr2_hdw *hdw = urb->context;
3553 hdw->ctl_read_pend_flag = 0;
3554 if (hdw->ctl_write_pend_flag) return;
3555 complete(&hdw->ctl_done);
3560 struct pvr2_hdw *hdw;
3566 struct pvr2_hdw *hdw = timer->hdw;
3568 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3569 hdw->ctl_timeout_flag = !0;
3570 if (hdw->ctl_write_pend_flag)
3571 usb_unlink_urb(hdw->ctl_write_urb);
3572 if (hdw->ctl_read_pend_flag)
3573 usb_unlink_urb(hdw->ctl_read_urb);
3582 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3590 .hdw = hdw,
3593 if (!hdw->ctl_lock_held) {
3598 if (!hdw->flag_ok && !probe_fl) {
3603 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3636 hdw->cmd_debug_state = 1;
3638 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3640 hdw->cmd_debug_code = 0;
3641 hdw->cmd_debug_write_len = write_len;
3642 hdw->cmd_debug_read_len = read_len;
3645 init_completion(&hdw->ctl_done);
3646 hdw->ctl_timeout_flag = 0;
3647 hdw->ctl_write_pend_flag = 0;
3648 hdw->ctl_read_pend_flag = 0;
3653 hdw->cmd_debug_state = 2;
3656 hdw->ctl_write_buffer[idx] =
3660 usb_fill_bulk_urb(hdw->ctl_write_urb,
3661 hdw->usb_dev,
3662 usb_sndbulkpipe(hdw->usb_dev,
3664 hdw->ctl_write_buffer,
3667 hdw);
3668 hdw->ctl_write_urb->actual_length = 0;
3669 hdw->ctl_write_pend_flag = !0;
3670 if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
3676 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3681 hdw->ctl_write_pend_flag = 0;
3687 hdw->cmd_debug_state = 3;
3688 memset(hdw->ctl_read_buffer,0x43,read_len);
3690 usb_fill_bulk_urb(hdw->ctl_read_urb,
3691 hdw->usb_dev,
3692 usb_rcvbulkpipe(hdw->usb_dev,
3694 hdw->ctl_read_buffer,
3697 hdw);
3698 hdw->ctl_read_urb->actual_length = 0;
3699 hdw->ctl_read_pend_flag = !0;
3700 if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
3706 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3711 hdw->ctl_read_pend_flag = 0;
3720 hdw->cmd_debug_state = 4;
3721 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3722 wait_for_completion(&hdw->ctl_done);
3724 hdw->cmd_debug_state = 5;
3729 hdw->cmd_debug_state = 6;
3732 if (hdw->ctl_timeout_flag) {
3743 if ((hdw->ctl_write_urb->status != 0) &&
3744 (hdw->ctl_write_urb->status != -ENOENT) &&
3745 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3746 (hdw->ctl_write_urb->status != -ECONNRESET)) {
3749 status = hdw->ctl_write_urb->status;
3757 if (hdw->ctl_write_urb->actual_length < write_len) {
3764 hdw->ctl_write_urb->actual_length);
3771 if ((hdw->ctl_read_urb->status != 0) &&
3772 (hdw->ctl_read_urb->status != -ENOENT) &&
3773 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3774 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3777 status = hdw->ctl_read_urb->status;
3785 if (hdw->ctl_read_urb->actual_length < read_len) {
3792 hdw->ctl_read_urb->actual_length);
3799 hdw->ctl_read_buffer[idx];
3805 hdw->cmd_debug_state = 0;
3807 pvr2_hdw_render_useless(hdw);
3815 int pvr2_send_request(struct pvr2_hdw *hdw,
3819 return pvr2_send_request_ex(hdw,HZ*4,0,
3825 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3830 LOCK_TAKE(hdw->ctl_lock);
3831 hdw->cmd_buffer[0] = cmdcode & 0xffu;
3836 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3838 hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3864 " (%u",hdw->cmd_buffer[1]);
3869 ",%u",hdw->cmd_buffer[2]);
3879 ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3880 LOCK_GIVE(hdw->ctl_lock);
3885 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3889 LOCK_TAKE(hdw->ctl_lock);
3891 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3892 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3893 hdw->cmd_buffer[5] = 0;
3894 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3895 hdw->cmd_buffer[7] = reg & 0xff;
3898 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3900 LOCK_GIVE(hdw->ctl_lock);
3906 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3910 LOCK_TAKE(hdw->ctl_lock);
3912 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3913 hdw->cmd_buffer[1] = 0;
3914 hdw->cmd_buffer[2] = 0;
3915 hdw->cmd_buffer[3] = 0;
3916 hdw->cmd_buffer[4] = 0;
3917 hdw->cmd_buffer[5] = 0;
3918 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3919 hdw->cmd_buffer[7] = reg & 0xff;
3921 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3922 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3924 LOCK_GIVE(hdw->ctl_lock);
3930 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3932 if (!hdw->flag_ok) return;
3935 if (hdw->vid_stream) {
3936 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3938 hdw->flag_ok = 0;
3939 trace_stbit("flag_ok",hdw->flag_ok);
3940 pvr2_hdw_state_sched(hdw);
3944 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3948 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3950 ret = usb_reset_device(hdw->usb_dev);
3951 usb_unlock_device(hdw->usb_dev);
3966 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3972 if (!hdw->usb_dev) return;
3988 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3989 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,1000);
3993 pvr2_hdw_render_useless(hdw);
4000 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4002 return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4006 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4008 return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4013 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4017 if (hdw->decoder_client_id) {
4018 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4020 pvr2_hdw_cx25840_vbi_hack(hdw);
4029 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4031 hdw->flag_ok = !0;
4034 if (le16_to_cpu(hdw->usb_dev->descriptor.idVendor) == 0x2040 &&
4035 (le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7502 ||
4036 le16_to_cpu(hdw->usb_dev->descriptor.idProduct) == 0x7510)) {
4040 return pvr2_issue_simple_cmd(hdw,
4046 return pvr2_issue_simple_cmd(hdw,
4053 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4055 hdw->flag_ok = !0;
4056 return pvr2_issue_simple_cmd(hdw,(onoff ?
4062 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4065 return pvr2_issue_simple_cmd(hdw,(onoff ?
4071 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4077 if (cmode == hdw->pathway_state) {
4082 switch (hdw->hdw_desc->digital_control_scheme) {
4084 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4090 pvr2_hdw_cmd_decoder_reset(hdw);
4097 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4102 pvr2_hdw_untrip_unlocked(hdw);
4103 hdw->pathway_state = cmode;
4107 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4116 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4118 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4120 pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4132 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4137 if ((!onoff) == (!hdw->led_on)) return;
4139 hdw->led_on = onoff != 0;
4141 scheme_id = hdw->hdw_desc->led_scheme;
4148 if (fp) (*fp)(hdw,onoff);
4153 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4159 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4160 return pvr2_issue_simple_cmd(hdw,
4167 if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4176 switch (hdw->hdw_desc->digital_control_scheme) {
4178 return pvr2_issue_simple_cmd(hdw,
4183 ret = pvr2_issue_simple_cmd(hdw,
4188 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4196 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4198 if (hdw->state_pathway_ok) {
4202 if (!hdw->state_pipeline_idle) {
4206 pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4207 hdw->state_pathway_ok = !0;
4208 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4214 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4216 if (hdw->state_encoder_ok) return 0;
4217 if (hdw->flag_tripped) return 0;
4218 if (hdw->state_encoder_run) return 0;
4219 if (hdw->state_encoder_config) return 0;
4220 if (hdw->state_decoder_run) return 0;
4221 if (hdw->state_usbstream_run) return 0;
4222 if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4223 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4224 } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4228 if (pvr2_upload_firmware2(hdw) < 0) {
4229 hdw->flag_tripped = !0;
4230 trace_stbit("flag_tripped",hdw->flag_tripped);
4233 hdw->state_encoder_ok = !0;
4234 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4240 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4242 if (hdw->state_encoder_config) {
4243 if (hdw->state_encoder_ok) {
4244 if (hdw->state_pipeline_req &&
4245 !hdw->state_pipeline_pause) return 0;
4247 hdw->state_encoder_config = 0;
4248 hdw->state_encoder_waitok = 0;
4249 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4251 del_timer_sync(&hdw->encoder_wait_timer);
4253 if (!hdw->state_pathway_ok ||
4254 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4255 !hdw->state_encoder_ok ||
4256 !hdw->state_pipeline_idle ||
4257 hdw->state_pipeline_pause ||
4258 !hdw->state_pipeline_req ||
4259 !hdw->state_pipeline_config) {
4263 if (timer_pending(&hdw->encoder_wait_timer)) {
4264 del_timer_sync(&hdw->encoder_wait_timer);
4266 if (hdw->state_encoder_waitok) {
4270 hdw->state_encoder_waitok = 0;
4272 hdw->state_encoder_waitok);
4277 if (!hdw->state_encoder_waitok) {
4278 if (!timer_pending(&hdw->encoder_wait_timer)) {
4285 if (!hdw->state_encoder_waitok) {
4286 hdw->encoder_wait_timer.expires =
4289 add_timer(&hdw->encoder_wait_timer);
4297 pvr2_encoder_configure(hdw);
4298 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4300 trace_stbit("state_encoder_config",hdw->state_encoder_config);
4306 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4308 if (!hdw->state_encoder_ok) {
4312 if (!hdw->state_pathway_ok) {
4318 switch (hdw->pathway_state) {
4320 if (!hdw->state_decoder_run) {
4328 if (hdw->state_encoder_runok) {
4351 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4353 if (!hdw->state_encoder_ok) {
4357 if (!hdw->state_pathway_ok) {
4363 switch (hdw->pathway_state) {
4365 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4372 if ((hdw->hdw_desc->digital_control_scheme ==
4374 !hdw->state_encoder_runok) {
4397 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4399 if (hdw->state_encoder_run) {
4400 if (!state_check_disable_encoder_run(hdw)) return 0;
4401 if (hdw->state_encoder_ok) {
4402 del_timer_sync(&hdw->encoder_run_timer);
4403 if (pvr2_encoder_stop(hdw) < 0) return !0;
4405 hdw->state_encoder_run = 0;
4407 if (!state_check_enable_encoder_run(hdw)) return 0;
4408 if (pvr2_encoder_start(hdw) < 0) return !0;
4409 hdw->state_encoder_run = !0;
4410 if (!hdw->state_encoder_runok) {
4411 hdw->encoder_run_timer.expires = jiffies +
4413 add_timer(&hdw->encoder_run_timer);
4416 trace_stbit("state_encoder_run",hdw->state_encoder_run);
4424 struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4425 hdw->state_decoder_quiescent = !0;
4426 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4427 hdw->state_stale = !0;
4428 schedule_work(&hdw->workpoll);
4435 struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4436 hdw->state_decoder_ready = !0;
4437 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4438 hdw->state_stale = !0;
4439 schedule_work(&hdw->workpoll);
4446 struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4447 hdw->state_encoder_waitok = !0;
4448 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4449 hdw->state_stale = !0;
4450 schedule_work(&hdw->workpoll);
4457 struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4458 if (!hdw->state_encoder_runok) {
4459 hdw->state_encoder_runok = !0;
4460 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4461 hdw->state_stale = !0;
4462 schedule_work(&hdw->workpoll);
4468 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4470 if (hdw->state_decoder_run) {
4471 if (hdw->state_encoder_ok) {
4472 if (hdw->state_pipeline_req &&
4473 !hdw->state_pipeline_pause &&
4474 hdw->state_pathway_ok) return 0;
4476 if (!hdw->flag_decoder_missed) {
4477 pvr2_decoder_enable(hdw,0);
4479 hdw->state_decoder_quiescent = 0;
4480 hdw->state_decoder_run = 0;
4482 del_timer_sync(&hdw->quiescent_timer);
4486 del_timer_sync(&hdw->decoder_stabilization_timer);
4487 hdw->state_decoder_ready = 0;
4489 if (!hdw->state_decoder_quiescent) {
4490 if (!timer_pending(&hdw->quiescent_timer)) {
4501 if (!hdw->state_decoder_quiescent) {
4502 hdw->quiescent_timer.expires =
4505 add_timer(&hdw->quiescent_timer);
4513 if (!hdw->state_pathway_ok ||
4514 (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4515 !hdw->state_pipeline_req ||
4516 hdw->state_pipeline_pause ||
4517 !hdw->state_pipeline_config ||
4518 !hdw->state_encoder_config ||
4519 !hdw->state_encoder_ok) return 0;
4520 del_timer_sync(&hdw->quiescent_timer);
4521 if (hdw->flag_decoder_missed) return 0;
4522 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4523 hdw->state_decoder_quiescent = 0;
4524 hdw->state_decoder_ready = 0;
4525 hdw->state_decoder_run = !0;
4526 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4527 hdw->decoder_stabilization_timer.expires =
4530 add_timer(&hdw->decoder_stabilization_timer);
4532 hdw->state_decoder_ready = !0;
4535 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4536 trace_stbit("state_decoder_run",hdw->state_decoder_run);
4537 trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4543 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4545 if (hdw->state_usbstream_run) {
4547 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4548 fl = (hdw->state_encoder_ok &&
4549 hdw->state_encoder_run);
4550 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4551 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4552 fl = hdw->state_encoder_ok;
4555 hdw->state_pipeline_req &&
4556 !hdw->state_pipeline_pause &&
4557 hdw->state_pathway_ok) {
4560 pvr2_hdw_cmd_usbstream(hdw,0);
4561 hdw->state_usbstream_run = 0;
4563 if (!hdw->state_pipeline_req ||
4564 hdw->state_pipeline_pause ||
4565 !hdw->state_pathway_ok) return 0;
4566 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4567 if (!hdw->state_encoder_ok ||
4568 !hdw->state_encoder_run) return 0;
4569 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4570 (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4571 if (!hdw->state_encoder_ok) return 0;
4572 if (hdw->state_encoder_run) return 0;
4573 if (hdw->hdw_desc->digital_control_scheme ==
4580 if (!hdw->state_encoder_runok) return 0;
4583 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4584 hdw->state_usbstream_run = !0;
4586 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4592 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4594 if (hdw->state_pipeline_config ||
4595 hdw->state_pipeline_pause) return 0;
4596 pvr2_hdw_commit_execute(hdw);
4604 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4609 st = !(hdw->state_encoder_run ||
4610 hdw->state_decoder_run ||
4611 hdw->state_usbstream_run ||
4612 (!hdw->state_decoder_quiescent));
4613 if (!st != !hdw->state_pipeline_idle) {
4614 hdw->state_pipeline_idle = st;
4617 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4618 hdw->state_pipeline_pause = 0;
4640 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4646 if (!hdw->state_stale) return 0;
4647 if ((hdw->fw1_state != FW1_STATE_OK) ||
4648 !hdw->flag_ok) {
4649 hdw->state_stale = 0;
4661 state_update_pipeline_state(hdw);
4663 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4664 if ((*eval_funcs[i])(hdw)) {
4667 state_update_pipeline_state(hdw);
4670 } while (check_flag && hdw->flag_ok);
4671 hdw->state_stale = 0;
4672 trace_stbit("state_stale",hdw->state_stale);
4705 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4713 (hdw->flag_ok ? " <ok>" : " <fail>"),
4714 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4715 (hdw->flag_disconnected ? " <disconnected>" :
4717 (hdw->flag_tripped ? " <tripped>" : ""),
4718 (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4719 pvr2_pathway_state_name(hdw->pathway_state));
4725 (hdw->state_pipeline_idle ? " <idle>" : ""),
4726 (hdw->state_pipeline_config ?
4728 (hdw->state_pipeline_req ? " <req>" : ""),
4729 (hdw->state_pipeline_pause ? " <pause>" : ""));
4734 (hdw->state_decoder_run ?
4735 (hdw->state_decoder_ready ?
4737 (hdw->state_decoder_quiescent ?
4739 (hdw->state_decoder_quiescent ?
4741 (hdw->state_encoder_ok ?
4743 (hdw->state_encoder_run ?
4744 (hdw->state_encoder_runok ?
4747 (hdw->state_encoder_runok ?
4750 (hdw->state_encoder_config ?
4752 (hdw->state_encoder_waitok ?
4754 (hdw->state_usbstream_run ?
4756 (hdw->state_pathway_ok ?
4762 pvr2_get_state_name(hdw->master_state));
4771 tcnt += print_input_mask(hdw->input_avail_mask,
4774 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4779 tcnt += print_input_mask(hdw->input_allowed_mask,
4787 if (!hdw->vid_stream) break;
4788 pvr2_stream_get_stats(hdw->vid_stream,
4802 unsigned int id = hdw->ir_scheme_active;
4816 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4828 v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4856 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4861 LOCK_TAKE(hdw->big_lock);
4863 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4870 ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4872 LOCK_GIVE(hdw->big_lock);
4877 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4884 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4886 pr_info("%s %.*s\n", hdw->name, ccnt, buf);
4888 ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4898 pr_info("%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4906 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4916 pvr2_hdw_state_log_state(hdw);
4920 state_updated = pvr2_hdw_state_update(hdw);
4922 analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4925 if (!hdw->flag_ok) {
4927 } else if (hdw->fw1_state != FW1_STATE_OK) {
4930 hdw->hdw_desc->flag_digital_requires_cx23416) &&
4931 !hdw->state_encoder_ok) {
4933 } else if (hdw->flag_tripped ||
4934 (analog_mode && hdw->flag_decoder_missed)) {
4936 } else if (hdw->state_usbstream_run &&
4938 (hdw->state_encoder_run && hdw->state_decoder_run))) {
4943 if (hdw->master_state != st) {
4946 pvr2_get_state_name(hdw->master_state),
4948 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4949 hdw->master_state = st;
4955 wake_up(&hdw->state_wait_data);
4959 pvr2_hdw_state_log_state(hdw);
4969 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4971 if (hdw->state_stale) return;
4972 hdw->state_stale = !0;
4973 trace_stbit("state_stale",hdw->state_stale);
4974 schedule_work(&hdw->workpoll);
4978 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4980 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4984 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4986 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4990 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4992 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4996 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5001 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5012 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5016 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5021 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5032 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5036 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5038 struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5040 vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5042 hdw->tuner_signal_stale = 0;
5047 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5055 hdw->cropcap_stale = 0;
5059 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5061 return hdw->input_avail_mask;
5065 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5067 return hdw->input_allowed_mask;
5071 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5073 if (hdw->input_val != v) {
5074 hdw->input_val = v;
5075 hdw->input_dirty = !0;
5081 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5082 hdw->freqSelector = 0;
5083 hdw->freqDirty = !0;
5084 } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5085 (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5086 hdw->freqSelector = 1;
5087 hdw->freqDirty = !0;
5093 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5099 LOCK_TAKE(hdw->big_lock);
5101 nv = hdw->input_allowed_mask & ~change_mask;
5103 nv &= hdw->input_avail_mask;
5109 hdw->input_allowed_mask = nv;
5110 if ((1UL << hdw->input_val) & hdw->input_allowed_mask) {
5117 if (!hdw->input_allowed_mask) {
5121 m = hdw->input_allowed_mask;
5124 pvr2_hdw_set_input(hdw,idx);
5128 LOCK_GIVE(hdw->big_lock);
5134 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5137 LOCK_TAKE(hdw->ctl_lock); do {
5138 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5139 result = pvr2_send_request(hdw,
5140 hdw->cmd_buffer,1,
5141 hdw->cmd_buffer,1);
5143 result = hdw->cmd_buffer[0];
5144 } while(0); LOCK_GIVE(hdw->ctl_lock);