Lines Matching defs:hdw

12 #include "pvrusb2-hdw-internal.h"
26 static int pvr2_encoder_write_words(struct pvr2_hdw *hdw,
48 memset(hdw->cmd_buffer,0,sizeof(hdw->cmd_buffer));
50 hdw->cmd_buffer[bAddr++] = FX2CMD_MEM_WRITE_DWORD;
53 hdw->cmd_buffer[bAddr+6] = (addr & 0xffu);
54 hdw->cmd_buffer[bAddr+5] = ((addr>>8) & 0xffu);
55 hdw->cmd_buffer[bAddr+4] = ((addr>>16) & 0xffu);
56 PVR2_DECOMPOSE_LE(hdw->cmd_buffer, bAddr,data[idx]);
59 ret = pvr2_send_request(hdw,
60 hdw->cmd_buffer,1+(chunkCnt*7),
72 static int pvr2_encoder_read_words(struct pvr2_hdw *hdw,
94 hdw->cmd_buffer[0] =
97 hdw->cmd_buffer[1] = 0;
98 hdw->cmd_buffer[2] = 0;
99 hdw->cmd_buffer[3] = 0;
100 hdw->cmd_buffer[4] = 0;
101 hdw->cmd_buffer[5] = ((offs>>16) & 0xffu);
102 hdw->cmd_buffer[6] = ((offs>>8) & 0xffu);
103 hdw->cmd_buffer[7] = (offs & 0xffu);
104 ret = pvr2_send_request(hdw,
105 hdw->cmd_buffer,8,
106 hdw->cmd_buffer,
111 data[idx] = PVR2_COMPOSE_LE(hdw->cmd_buffer,idx*4);
141 struct pvr2_hdw *hdw = (struct pvr2_hdw *)ctxt;
191 LOCK_TAKE(hdw->ctl_lock);
193 if (!hdw->state_encoder_ok) {
212 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,idx);
215 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
220 ret = pvr2_encoder_read_words(hdw,MBOX_BASE,rdData,
260 del_timer_sync(&hdw->encoder_run_timer);
261 hdw->state_encoder_ok = 0;
265 (hdw->state_encoder_ok ? "true" : "false"));
266 if (hdw->state_encoder_runok) {
267 hdw->state_encoder_runok = 0;
271 (hdw->state_encoder_runok ?
285 ret = pvr2_encoder_write_words(hdw,MBOX_BASE,wrData,1);
288 LOCK_GIVE(hdw->ctl_lock);
294 static int pvr2_encoder_vcmd(struct pvr2_hdw *hdw, int cmd,
315 return pvr2_encoder_cmd(hdw,cmd,args,0,data);
321 static int pvr2_encoder_prep_config(struct pvr2_hdw *hdw)
332 LOCK_TAKE(hdw->ctl_lock); do {
335 pvr2_encoder_write_words(hdw,0x01fe,dat,1);
336 pvr2_encoder_write_words(hdw,0x023e,dat,1);
337 } while(0); LOCK_GIVE(hdw->ctl_lock);
352 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 5,0,0,0);
360 if (hdw->hdw_desc->flag_has_cx25840) {
365 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 3,
368 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 8,0,0,0);
376 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 4,1,0,0);
379 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4, 0,3,0,0);
380 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC,4,15,0,0,0);
384 ret |= pvr2_encoder_vcmd(hdw, CX2341X_ENC_MISC, 2, 4, 1);
389 int pvr2_encoder_adjust(struct pvr2_hdw *hdw)
392 ret = cx2341x_update(hdw,pvr2_encoder_cmd,
393 (hdw->enc_cur_valid ? &hdw->enc_cur_state : NULL),
394 &hdw->enc_ctl_state);
399 hdw->enc_cur_state = hdw->enc_ctl_state;
400 hdw->enc_cur_valid = !0;
406 int pvr2_encoder_configure(struct pvr2_hdw *hdw)
411 hdw->enc_ctl_state.port = CX2341X_PORT_STREAMING;
412 hdw->enc_ctl_state.width = hdw->res_hor_val;
413 hdw->enc_ctl_state.height = hdw->res_ver_val;
414 hdw->enc_ctl_state.is_50hz = ((hdw->std_mask_cur & V4L2_STD_525_60) ?
419 ret |= pvr2_encoder_prep_config(hdw);
423 if (hdw->hdw_desc->flag_has_cx25840) {
429 hdw,CX2341X_ENC_SET_NUM_VSYNC_LINES, 2,
434 hdw,CX2341X_ENC_SET_EVENT_NOTIFICATION, 4,
438 hdw,CX2341X_ENC_SET_VBI_LINE, 5,
447 ret = pvr2_encoder_adjust(hdw);
451 hdw, CX2341X_ENC_INITIALIZE_INPUT, 0);
463 int pvr2_encoder_start(struct pvr2_hdw *hdw)
468 pvr2_write_register(hdw, 0x0048, 0xbfffffff);
470 pvr2_encoder_vcmd(hdw,CX2341X_ENC_MUTE_VIDEO,1,
471 hdw->input_val == PVR2_CVAL_INPUT_RADIO ? 1 : 0);
473 switch (hdw->active_stream_type) {
475 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
479 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
483 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_START_CAPTURE,2,
490 int pvr2_encoder_stop(struct pvr2_hdw *hdw)
495 pvr2_write_register(hdw, 0x0048, 0xffffffff);
497 switch (hdw->active_stream_type) {
499 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
503 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,
507 status = pvr2_encoder_vcmd(hdw,CX2341X_ENC_STOP_CAPTURE,3,