Lines Matching defs:ir
21 #define DRIVER_NAME "meson-ir"
188 static void meson_ir_nec_handler(struct meson_ir *ir)
194 regmap_read(ir->reg, IR_DEC_STATUS, &status);
197 rc_repeat(ir->rc);
199 regmap_read(ir->reg, IR_DEC_FRAME, &code);
203 rc_keydown(ir->rc, proto, code, 0);
207 static void meson_ir_hw_handler(struct meson_ir *ir)
209 if (ir->rc->enabled_protocols & RC_PROTO_BIT_NEC)
210 meson_ir_nec_handler(ir);
215 struct meson_ir *ir = dev_id;
219 spin_lock(&ir->lock);
221 regmap_read(ir->reg, IR_DEC_STATUS, &status);
223 if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
226 regmap_read(ir->reg, IR_DEC_REG1, &duration);
230 ir_raw_event_store_with_timeout(ir->rc, &rawir);
231 } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
233 meson_ir_hw_handler(ir);
236 spin_unlock(&ir->lock);
248 struct meson_ir *ir = dev->priv;
266 spin_lock_irqsave(&ir->lock, flags);
269 regmap_read(ir->reg, IR_DEC_STATUS, ®val);
270 regmap_read(ir->reg, IR_DEC_FRAME, ®val);
272 /* Reset ir decoder and disable decoder */
273 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
274 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
279 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME, regval);
282 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FILTER,
287 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE, regval);
290 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_HOLD_CODE,
295 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_BIT_ORDER,
299 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_TICK_MODE,
308 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_COUNTER,
311 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_REPEAT_TIME,
314 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_COMPARE_FRAME,
324 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_FRAME_TIME_MAX,
329 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_FRAME_LEN, regval);
336 regmap_update_bits(ir->reg, IR_DEC_LDR_ACTIVE, IR_DEC_LDR_ACTIVE_MAX |
342 regmap_update_bits(ir->reg, IR_DEC_LDR_IDLE,
348 regmap_update_bits(ir->reg, IR_DEC_LDR_REPEAT, IR_DEC_LDR_REPEAT_MAX |
357 regmap_update_bits(ir->reg, IR_DEC_BIT_0,
366 regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_MAX |
370 regmap_update_bits(ir->reg, IR_DEC_STATUS, IR_DEC_STATUS_BIT_1_ENABLE,
380 regmap_update_bits(ir->reg, IR_DEC_DURATN2,
389 regmap_update_bits(ir->reg, IR_DEC_DURATN3,
392 /* Reset ir decoder and enable decode */
393 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
395 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
396 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
399 spin_unlock_irqrestore(&ir->lock, flags);
409 struct meson_ir *ir = dev->priv;
411 spin_lock_irqsave(&ir->lock, flags);
414 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET,
416 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
419 if (of_device_is_compatible(dev->dev.of_node, "amlogic,meson6-ir"))
420 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
424 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
429 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
433 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
436 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
439 spin_unlock_irqrestore(&ir->lock, flags);
451 struct meson_ir *ir;
454 ir = devm_kzalloc(dev, sizeof(struct meson_ir), GFP_KERNEL);
455 if (!ir)
462 ir->param = match_data;
468 meson_ir_regmap_config.max_register = ir->param->max_register;
469 ir->reg = devm_regmap_init_mmio(&pdev->dev, res_start,
471 if (IS_ERR(ir->reg))
472 return PTR_ERR(ir->reg);
478 if (ir->param->support_hw_decoder)
479 ir->rc = devm_rc_allocate_device(&pdev->dev,
482 ir->rc = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
484 if (!ir->rc) {
489 if (ir->rc->driver_type == RC_DRIVER_IR_RAW) {
490 ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
491 ir->rc->rx_resolution = MESON_RAW_TRATE;
492 ir->rc->min_timeout = 1;
493 ir->rc->timeout = IR_DEFAULT_TIMEOUT;
494 ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
495 } else if (ir->rc->driver_type == RC_DRIVER_SCANCODE) {
496 ir->rc->allowed_protocols = RC_PROTO_BIT_NEC;
497 ir->rc->change_protocol = meson_ir_hw_decoder_init;
500 ir->rc->priv = ir;
501 ir->rc->device_name = DRIVER_NAME;
502 ir->rc->input_phys = DRIVER_NAME "/input0";
503 ir->rc->input_id.bustype = BUS_HOST;
505 ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
506 ir->rc->driver_name = DRIVER_NAME;
508 spin_lock_init(&ir->lock);
509 platform_set_drvdata(pdev, ir);
511 ret = devm_rc_register_device(dev, ir->rc);
517 if (ir->rc->driver_type == RC_DRIVER_IR_RAW)
518 meson_ir_sw_decoder_init(ir->rc);
520 ret = devm_request_irq(dev, irq, meson_ir_irq, 0, "meson_ir", ir);
533 struct meson_ir *ir = platform_get_drvdata(pdev);
537 spin_lock_irqsave(&ir->lock, flags);
538 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
539 spin_unlock_irqrestore(&ir->lock, flags);
546 struct meson_ir *ir = platform_get_drvdata(pdev);
549 spin_lock_irqsave(&ir->lock, flags);
555 if (of_device_is_compatible(node, "amlogic,meson6-ir"))
556 regmap_update_bits(ir->reg, IR_DEC_REG1, IR_DEC_REG1_MODE,
559 regmap_update_bits(ir->reg, IR_DEC_REG2, IR_DEC_REG2_MODE,
563 regmap_update_bits(ir->reg, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
567 spin_unlock_irqrestore(&ir->lock, flags);
587 .compatible = "amlogic,meson6-ir",
590 .compatible = "amlogic,meson8b-ir",
593 .compatible = "amlogic,meson-gxbb-ir",
596 .compatible = "amlogic,meson-s4-ir",