media/rc/ir-hix5hd2.c

119 static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
123 	if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
126 	writel_relaxed(val, priv->base + IR_ENABLE);
129 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
134 	hix5hd2_ir_enable(priv);
136 	while (readl_relaxed(priv->base + IR_BUSY)) {
140 			dev_err(priv->dev, "IR_BUSY timeout\n");
146 	rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
153 	writel_relaxed(val, priv->base + IR_CONFIG);
155 	writel_relaxed(0x00, priv->base + IR_INTM);
157 	writel_relaxed(0x01, priv->base + IR_START);
163 	struct hix5hd2_ir_priv *priv = rdev->priv;
166 	ret = hix5hd2_ir_clk_enable(priv, true);
170 	ret = hix5hd2_ir_config(priv);
172 		hix5hd2_ir_clk_enable(priv, false);
180 	struct hix5hd2_ir_priv *priv = rdev->priv;
182 	hix5hd2_ir_clk_enable(priv, false);
190 	struct hix5hd2_ir_priv *priv = data;
192 	irq_sr = readl_relaxed(priv->base + IR_INTS);
199 		ir_raw_event_overflow(priv->rdev);
200 		symb_num = readl_relaxed(priv->base + IR_DATAH);
202 			readl_relaxed(priv->base + IR_DATAL);
204 		writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
205 		dev_info(priv->dev, "overflow, level=%d\n",
212 		symb_num = readl_relaxed(priv->base + IR_DATAH);
214 			symb_val = readl_relaxed(priv->base + IR_DATAL);
221 			ir_raw_event_store(priv->rdev, &ev);
226 				ir_raw_event_store(priv->rdev, &ev);
228 				ir_raw_event_set_idle(priv->rdev, true);
233 			writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
235 			writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
239 	ir_raw_event_handle(priv->rdev);
254 	struct hix5hd2_ir_priv *priv;
259 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
260 	if (!priv)
263 	priv->socdata = device_get_match_data(dev);
264 	if (!priv->socdata) {
269 	priv->regmap = syscon_regmap_lookup_by_phandle(node,
271 	if (IS_ERR(priv->regmap)) {
273 		priv->regmap = NULL;
276 	priv->base = devm_platform_ioremap_resource(pdev, 0);
277 	if (IS_ERR(priv->base))
278 		return PTR_ERR(priv->base);
280 	priv->irq = platform_get_irq(pdev, 0);
281 	if (priv->irq < 0)
282 		return priv->irq;
288 	priv->clock = devm_clk_get(dev, NULL);
289 	if (IS_ERR(priv->clock)) {
291 		ret = PTR_ERR(priv->clock);
294 	ret = clk_prepare_enable(priv->clock);
297 	priv->rate = clk_get_rate(priv->clock);
300 	rdev->priv = priv;
319 	if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
320 			     0, pdev->name, priv) < 0) {
321 		dev_err(dev, "IRQ %d register failed\n", priv->irq);
326 	priv->rdev = rdev;
327 	priv->dev = dev;
328 	platform_set_drvdata(pdev, priv);
336 	clk_disable_unprepare(priv->clock);
345 	struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
347 	clk_disable_unprepare(priv->clock);
348 	rc_unregister_device(priv->rdev);
354 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
356 	clk_disable_unprepare(priv->clock);
357 	hix5hd2_ir_clk_enable(priv, false);
364 	struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
367 	ret = hix5hd2_ir_clk_enable(priv, true);
371 	ret = clk_prepare_enable(priv->clock);
373 		hix5hd2_ir_clk_enable(priv, false);
377 	hix5hd2_ir_enable(priv);
379 	writel_relaxed(0x00, priv->base + IR_INTM);
380 	writel_relaxed(0xff, priv->base + IR_INTC);
381 	writel_relaxed(0x01, priv->base + IR_START);