platform/verisilicon/hantro_hevc.c

30 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
32 	hevc_dec->ref_bufs_used = 0;
38 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
43 		if (hevc_dec->ref_bufs_poc[i] == poc) {
44 			hevc_dec->ref_bufs_used |= 1 << i;
45 			return hevc_dec->ref_bufs[i].dma;
54 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
59 		if (!(hevc_dec->ref_bufs_used & 1 << i)) {
60 			hevc_dec->ref_bufs_used |= 1 << i;
61 			hevc_dec->ref_bufs_poc[i] = poc;
62 			hevc_dec->ref_bufs[i].dma = addr;
73 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
74 	const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
82 	    num_tile_cols <= hevc_dec->num_tile_cols_allocated)
86 	if (hevc_dec->tile_filter.cpu) {
87 		dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
88 				  hevc_dec->tile_filter.cpu,
89 				  hevc_dec->tile_filter.dma);
90 		hevc_dec->tile_filter.cpu = NULL;
93 	if (hevc_dec->tile_sao.cpu) {
94 		dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
95 				  hevc_dec->tile_sao.cpu,
96 				  hevc_dec->tile_sao.dma);
97 		hevc_dec->tile_sao.cpu = NULL;
100 	if (hevc_dec->tile_bsd.cpu) {
101 		dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,
102 				  hevc_dec->tile_bsd.cpu,
103 				  hevc_dec->tile_bsd.dma);
104 		hevc_dec->tile_bsd.cpu = NULL;
108 	hevc_dec->tile_filter.cpu = dma_alloc_coherent(vpu->dev, size,
109 						       &hevc_dec->tile_filter.dma,
111 	if (!hevc_dec->tile_filter.cpu)
113 	hevc_dec->tile_filter.size = size;
116 	hevc_dec->tile_sao.cpu = dma_alloc_coherent(vpu->dev, size,
117 						    &hevc_dec->tile_sao.dma,
119 	if (!hevc_dec->tile_sao.cpu)
121 	hevc_dec->tile_sao.size = size;
124 	hevc_dec->tile_bsd.cpu = dma_alloc_coherent(vpu->dev, size,
125 						    &hevc_dec->tile_bsd.dma,
127 	if (!hevc_dec->tile_bsd.cpu)
129 	hevc_dec->tile_bsd.size = size;
131 	hevc_dec->num_tile_cols_allocated = num_tile_cols;
136 	if (hevc_dec->tile_sao.cpu)
137 		dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
138 				  hevc_dec->tile_sao.cpu,
139 				  hevc_dec->tile_sao.dma);
140 	hevc_dec->tile_sao.cpu = NULL;
143 	if (hevc_dec->tile_filter.cpu)
144 		dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
145 				  hevc_dec->tile_filter.cpu,
146 				  hevc_dec->tile_filter.dma);
147 	hevc_dec->tile_filter.cpu = NULL;
173 	struct hantro_hevc_dec_hw_ctx *hevc_ctx = &ctx->hevc_dec;
213 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
215 	if (hevc_dec->tile_sizes.cpu)
216 		dma_free_coherent(vpu->dev, hevc_dec->tile_sizes.size,
217 				  hevc_dec->tile_sizes.cpu,
218 				  hevc_dec->tile_sizes.dma);
219 	hevc_dec->tile_sizes.cpu = NULL;
221 	if (hevc_dec->scaling_lists.cpu)
222 		dma_free_coherent(vpu->dev, hevc_dec->scaling_lists.size,
223 				  hevc_dec->scaling_lists.cpu,
224 				  hevc_dec->scaling_lists.dma);
225 	hevc_dec->scaling_lists.cpu = NULL;
227 	if (hevc_dec->tile_filter.cpu)
228 		dma_free_coherent(vpu->dev, hevc_dec->tile_filter.size,
229 				  hevc_dec->tile_filter.cpu,
230 				  hevc_dec->tile_filter.dma);
231 	hevc_dec->tile_filter.cpu = NULL;
233 	if (hevc_dec->tile_sao.cpu)
234 		dma_free_coherent(vpu->dev, hevc_dec->tile_sao.size,
235 				  hevc_dec->tile_sao.cpu,
236 				  hevc_dec->tile_sao.dma);
237 	hevc_dec->tile_sao.cpu = NULL;
239 	if (hevc_dec->tile_bsd.cpu)
240 		dma_free_coherent(vpu->dev, hevc_dec->tile_bsd.size,
241 				  hevc_dec->tile_bsd.cpu,
242 				  hevc_dec->tile_bsd.dma);
243 	hevc_dec->tile_bsd.cpu = NULL;
249 	struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
252 	memset(hevc_dec, 0, sizeof(*hevc_dec));
260 	hevc_dec->tile_sizes.cpu = dma_alloc_coherent(vpu->dev, size,
261 						      &hevc_dec->tile_sizes.dma,
263 	if (!hevc_dec->tile_sizes.cpu)
266 	hevc_dec->tile_sizes.size = size;
268 	hevc_dec->scaling_lists.cpu = dma_alloc_coherent(vpu->dev, SCALING_LIST_SIZE,
269 							 &hevc_dec->scaling_lists.dma,
271 	if (!hevc_dec->scaling_lists.cpu)
274 	hevc_dec->scaling_lists.size = SCALING_LIST_SIZE;