sti/c8sectpfe/c8sectpfe-core.c

66 	struct channel_info *channel;
71 		channel = fei->channel_data[chan_num];
74 		if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE))
75 			tasklet_schedule(&channel->tsklet);
84 	struct channel_info *channel = from_tasklet(channel, t, tsklet);
90 	if (unlikely(!channel || !channel->irec))
93 	fei = channel->fei;
95 	wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0));
96 	rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0));
98 	pos = rp - channel->back_buffer_busaddr;
102 		wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE;
113 	buf = channel->back_buffer_aligned;
116 		"chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n",
117 		channel->tsin_id, channel, num_packets, buf, pos, rp, wp);
122 				demux[channel->demux_mapping].dvb_demux,
129 	if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE))
130 		writel(channel->back_buffer_busaddr, channel->irec +
133 		writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0));
141 	struct channel_info *channel;
180 	channel = fei->channel_data[stdemux->tsin_index];
182 	bitmap = channel->pid_buffer_aligned;
186 		tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
188 		writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
196 					channel->pid_buffer_busaddr,
200 	channel->active = 1;
211 		dev_dbg(fei->dev, "Starting channel=%p\n", channel);
213 		tasklet_setup(&channel->tsklet, channel_swdemux_tsklet);
216 		writel(channel->fifo,
217 			fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id));
218 		writel(channel->fifo + FIFO_LEN - 1,
219 			fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id));
221 		writel(channel->fifo,
222 			fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id));
223 		writel(channel->fifo,
224 			fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id));
227 		/* reset read / write memdma ptrs for this channel */
228 		writel(channel->back_buffer_busaddr, channel->irec +
231 		tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
232 		writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
234 		writel(channel->back_buffer_busaddr, channel->irec +
239 			, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
242 		writel(0x1, channel->irec + DMA_PRDS_TPENABLE);
262 	struct channel_info *channel;
276 	channel = fei->channel_data[stdemux->tsin_index];
278 	bitmap = channel->pid_buffer_aligned;
281 		tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
283 		writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id));
290 					channel->pid_buffer_busaddr,
296 		channel = fei->channel_data[stdemux->tsin_index];
301 		writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id));
304 		writel(0,  channel->irec + DMA_PRDS_TPENABLE);
306 		tasklet_disable(&channel->tsklet);
308 		/* now request memdma channel goes idle */
309 		idlereq = (1 << channel->tsin_id) | IDLEREQ;
313 		ret = wait_for_completion_timeout(&channel->idle_completion,
319 				channel->tsin_id);
321 		reinit_completion(&channel->idle_completion);
323 		/* reset read / write ptrs for this channel */
325 		writel(channel->back_buffer_busaddr,
326 			channel->irec + DMA_PRDS_BUSBASE_TP(0));
328 		tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1;
329 		writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0));
331 		writel(channel->back_buffer_busaddr,
332 			channel->irec + DMA_PRDS_BUSWP_TP(0));
335 			"%s:%d stopping DMA feed on stdemux=%p channel=%d\n",
336 			__func__, __LINE__, stdemux, channel->tsin_id);
339 		memset(channel->pid_buffer_aligned, 0, PID_TABLE_SIZE);
343 					channel->pid_buffer_busaddr,
347 		channel->active = 0;
458 	dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n"
612 	/* advance pointer record block to our channel */
831 			"channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n",
868 	struct channel_info *channel;
879 		channel = fei->channel_data[i];
880 		free_input_block(fei, channel);