Lines Matching refs:ctx
46 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
54 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
60 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
62 struct s5p_mfc_dev *dev = ctx->dev;
67 mb_width = MB_WIDTH(ctx->img_width);
68 mb_height = MB_HEIGHT(ctx->img_height);
69 width64 = ALIGN(ctx->img_width, 64);
70 height32 = ALIGN(ctx->img_height, 32);
72 if (ctx->type == MFCINST_DECODER) {
74 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
75 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
76 } else if (ctx->type == MFCINST_ENCODER) {
78 ctx->tmv_buffer_size = 0;
80 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
84 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
88 lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
89 lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
90 if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC && ctx->is_10bit) {
91 ctx->luma_dpb_size =
94 if (ctx->is_422)
95 ctx->chroma_dpb_size =
96 ctx->luma_dpb_size;
98 ctx->chroma_dpb_size =
102 } else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC && ctx->is_10bit) {
103 ctx->luma_dpb_size =
104 ALIGN(ctx->img_width * 2, 128) * height32 + 64;
105 ctx->chroma_dpb_size =
106 ALIGN(ctx->img_width * 2, 128) * height32 / 2 + 64;
108 ctx->luma_dpb_size =
110 if (ctx->is_422)
111 ctx->chroma_dpb_size =
112 ctx->luma_dpb_size;
114 ctx->chroma_dpb_size =
117 ctx->luma_dpb_size = ALIGN(ctx->luma_dpb_size + 256, SZ_2K);
118 ctx->chroma_dpb_size = ALIGN(ctx->chroma_dpb_size + 256, SZ_2K);
120 lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
121 lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
122 if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
123 ctx->luma_dpb_size =
127 ctx->chroma_dpb_size =
132 ctx->luma_dpb_size =
136 ctx->chroma_dpb_size =
142 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
145 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
150 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
151 ctx->img_width, ctx->img_height,
155 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
156 ctx->img_width, ctx->img_height,
161 ctx->luma_dpb_size, ctx->chroma_dpb_size);
167 switch (ctx->codec_mode) {
173 ctx->scratch_buf_size =
178 ctx->scratch_buf_size =
182 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
184 ctx->bank1.size =
185 ctx->scratch_buf_size +
186 (ctx->mv_count * ctx->mv_size);
192 ctx->scratch_buf_size =
197 ctx->scratch_buf_size =
203 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
205 ctx->bank1.size = ctx->scratch_buf_size;
212 ctx->scratch_buf_size =
217 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
219 ctx->bank1.size = ctx->scratch_buf_size;
222 ctx->bank1.size = 0;
223 ctx->bank2.size = 0;
229 ctx->scratch_buf_size =
233 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
235 ctx->bank1.size = ctx->scratch_buf_size;
241 ctx->scratch_buf_size =
246 ctx->scratch_buf_size =
250 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
252 ctx->bank1.size = ctx->scratch_buf_size;
256 ctx->bank1.size =
257 ctx->scratch_buf_size +
258 (ctx->mv_count * ctx->mv_size);
262 ctx->bank1.size =
263 ctx->scratch_buf_size +
269 ctx->me_buffer_size =
273 ctx->me_buffer_size =
276 ctx->scratch_buf_size =
281 ctx->scratch_buf_size =
285 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
287 ctx->bank1.size =
288 ctx->scratch_buf_size + ctx->tmv_buffer_size +
289 (ctx->pb_count * (ctx->luma_dpb_size +
290 ctx->chroma_dpb_size + ctx->me_buffer_size));
291 ctx->bank2.size = 0;
297 ctx->me_buffer_size =
301 ctx->me_buffer_size =
305 ctx->scratch_buf_size =
309 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
311 ctx->bank1.size =
312 ctx->scratch_buf_size + ctx->tmv_buffer_size +
313 (ctx->pb_count * (ctx->luma_dpb_size +
314 ctx->chroma_dpb_size + ctx->me_buffer_size));
315 ctx->bank2.size = 0;
320 ctx->me_buffer_size =
324 ctx->me_buffer_size =
328 ctx->scratch_buf_size =
333 ctx->scratch_buf_size =
337 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
339 ctx->bank1.size =
340 ctx->scratch_buf_size + ctx->tmv_buffer_size +
341 (ctx->pb_count * (ctx->luma_dpb_size +
342 ctx->chroma_dpb_size + ctx->me_buffer_size));
343 ctx->bank2.size = 0;
347 ctx->me_buffer_size =
350 ctx->me_buffer_size =
353 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
354 ctx->bank1.size =
355 ctx->scratch_buf_size + ctx->tmv_buffer_size +
356 (ctx->pb_count * (ctx->luma_dpb_size +
357 ctx->chroma_dpb_size + ctx->me_buffer_size));
358 ctx->bank2.size = 0;
365 if (ctx->bank1.size > 0) {
366 ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);
371 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
377 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
379 s5p_mfc_release_generic_buf(ctx->dev, &ctx->bank1);
383 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
385 struct s5p_mfc_dev *dev = ctx->dev;
391 switch (ctx->codec_mode) {
395 ctx->ctx.size = buf_size->h264_dec_ctx;
404 ctx->ctx.size = buf_size->other_dec_ctx;
407 ctx->ctx.size = buf_size->h264_enc_ctx;
410 ctx->ctx.size = buf_size->hevc_enc_ctx;
415 ctx->ctx.size = buf_size->other_enc_ctx;
418 ctx->ctx.size = 0;
419 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
423 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->ctx);
429 memset(ctx->ctx.virt, 0, ctx->ctx.size);
438 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
440 s5p_mfc_release_priv_buf(ctx->dev, &ctx->ctx);
486 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
488 struct s5p_mfc_dev *dev = ctx->dev;
489 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
490 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
491 ctx->chroma_size_1 = 0;
493 "buffer dimensions: %dx%d\n", ctx->img_width,
494 ctx->img_height, ctx->buf_width, ctx->buf_height);
496 switch (ctx->dst_fmt->fourcc) {
499 ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
500 ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
501 ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
502 ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));
506 ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
507 ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);
508 ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12MT_HALIGN_V6);
509 ctx->luma_size = calc_plane(ctx->stride[0], ctx->img_height);
510 ctx->chroma_size = calc_plane(ctx->stride[1], (ctx->img_height / 2));
511 ctx->chroma_size_1 = calc_plane(ctx->stride[2], (ctx->img_height / 2));
515 if (IS_MFCV8_PLUS(ctx->dev)) {
517 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
518 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
519 ctx->chroma_size_1 += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
522 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
523 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
525 ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 1024);
527 ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 512);
529 ctx->mv_size = S5P_MFC_DEC_MV_SIZE(ctx->img_width, ctx->img_height, 128);
531 } else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
532 ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width, ctx->img_height);
533 ctx->mv_size = ALIGN(ctx->mv_size, 32);
535 ctx->mv_size = 0;
539 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
543 mb_width = MB_WIDTH(ctx->img_width);
544 mb_height = MB_HEIGHT(ctx->img_height);
546 if (IS_MFCV12(ctx->dev)) {
547 switch (ctx->src_fmt->fourcc) {
550 ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
551 ctx->stride[1] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
552 ctx->luma_size = ctx->stride[0] * ALIGN(ctx->img_height, 16);
553 ctx->chroma_size = ctx->stride[0] * ALIGN(ctx->img_height / 2, 16);
557 ctx->stride[0] = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
558 ctx->stride[1] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);
559 ctx->stride[2] = ALIGN(ctx->img_width / 2, S5P_FIMV_NV12M_HALIGN_V6);
560 ctx->luma_size = ctx->stride[0] * ALIGN(ctx->img_height, 16);
561 ctx->chroma_size = ctx->stride[1] * ALIGN(ctx->img_height / 2, 16);
562 ctx->chroma_size_1 = ctx->stride[2] * ALIGN(ctx->img_height / 2, 16);
565 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
566 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V12;
567 ctx->chroma_size_1 += MFC_CHROMA_PAD_BYTES_V12;
569 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
570 ctx->stride[0] = ctx->buf_width;
571 ctx->stride[1] = ctx->buf_width;
572 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
573 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
574 ctx->chroma_size_1 = 0;
576 if (IS_MFCV7_PLUS(ctx->dev)) {
577 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
578 ctx->chroma_size += MFC_LUMA_PAD_BYTES_V7;
584 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
588 struct s5p_mfc_dev *dev = ctx->dev;
595 ctx->inst_no, buf_addr, strm_size, strm_size);
606 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
610 struct s5p_mfc_dev *dev = ctx->dev;
616 buf_addr1 = ctx->bank1.dma;
617 buf_size1 = ctx->bank1.size;
620 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
621 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
623 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
624 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
625 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
626 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
628 writel(ctx->chroma_size_1, mfc_regs->d_third_plane_dpb_size);
630 writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
633 writel(ctx->stride[0], mfc_regs->d_first_plane_dpb_stride_size);
634 writel(ctx->stride[1], mfc_regs->d_second_plane_dpb_stride_size);
635 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
637 writel(ctx->stride[2], mfc_regs->d_third_plane_dpb_stride_size);
640 buf_addr1 += ctx->scratch_buf_size;
641 buf_size1 -= ctx->scratch_buf_size;
643 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
644 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||
645 ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {
646 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
647 writel(ctx->mv_count, mfc_regs->d_num_mv);
650 frame_size = ctx->luma_size;
651 frame_size_ch = ctx->chroma_size;
652 frame_size_mv = ctx->mv_size;
656 for (i = 0; i < ctx->total_dpb_count; i++) {
659 ctx->dst_bufs[i].cookie.raw.luma);
660 writel(ctx->dst_bufs[i].cookie.raw.luma,
663 ctx->dst_bufs[i].cookie.raw.chroma);
664 writel(ctx->dst_bufs[i].cookie.raw.chroma,
666 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
668 mfc_debug(2, "\tChroma_1 %d: %zx\n", i, ctx
670 writel(ctx->dst_bufs[i].cookie.raw.chroma_1, mfc_regs->d_third_plane_dpb +
674 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
675 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
676 ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
677 for (i = 0; i < ctx->mv_count; i++) {
691 if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
700 buf_addr1, buf_size1, ctx->total_dpb_count);
706 writel(ctx->inst_no, mfc_regs->instance_id);
715 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
718 struct s5p_mfc_dev *dev = ctx->dev;
730 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
734 struct s5p_mfc_dev *dev = ctx->dev;
746 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
750 struct s5p_mfc_dev *dev = ctx->dev;
756 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
770 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
772 struct s5p_mfc_dev *dev = ctx->dev;
779 buf_addr1 = ctx->bank1.dma;
780 buf_size1 = ctx->bank1.size;
786 for (i = 0; i < ctx->pb_count; i++) {
788 buf_addr1 += ctx->luma_dpb_size;
789 buf_size1 -= ctx->luma_dpb_size;
791 for (i = 0; i < ctx->pb_count; i++) {
793 buf_addr1 += ctx->chroma_dpb_size;
794 buf_size1 -= ctx->chroma_dpb_size;
796 for (i = 0; i < ctx->pb_count; i++) {
798 buf_addr1 += ctx->me_buffer_size;
799 buf_size1 -= ctx->me_buffer_size;
802 for (i = 0; i < ctx->pb_count; i++) {
804 buf_addr1 += ctx->luma_dpb_size;
806 buf_addr1 += ctx->chroma_dpb_size;
808 buf_addr1 += ctx->me_buffer_size;
809 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
810 + ctx->me_buffer_size);
815 writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
816 buf_addr1 += ctx->scratch_buf_size;
817 buf_size1 -= ctx->scratch_buf_size;
820 buf_addr1 += ctx->tmv_buffer_size >> 1;
822 buf_addr1 += ctx->tmv_buffer_size >> 1;
823 buf_size1 -= ctx->tmv_buffer_size;
826 buf_addr1, buf_size1, ctx->pb_count);
832 writel(ctx->inst_no, mfc_regs->instance_id);
841 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
843 struct s5p_mfc_dev *dev = ctx->dev;
848 writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
849 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
850 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
851 } else if (ctx->slice_mode ==
853 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
862 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
864 struct s5p_mfc_dev *dev = ctx->dev;
866 const struct s5p_mfc_enc_params *p = &ctx->enc_params;
872 writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
874 writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
877 writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
879 writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
890 ctx->slice_mode = p->slice_mode;
895 ctx->slice_size.mb = p->slice_mb;
899 ctx->slice_size.bits = p->slice_bit;
905 s5p_mfc_set_slice_mode(ctx);
922 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
929 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
936 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
943 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YVU420M) {
950 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M) {
1055 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
1057 struct s5p_mfc_dev *dev = ctx->dev;
1059 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1066 s5p_mfc_set_enc_params(ctx);
1075 if (ctx->img_width == 3840 && ctx->img_height == 2160) {
1149 writel(ctx->img_height >> 1,
1152 writel(ctx->img_height >> 1,
1348 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1350 struct s5p_mfc_dev *dev = ctx->dev;
1352 const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1358 s5p_mfc_set_enc_params(ctx);
1430 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1432 struct s5p_mfc_dev *dev = ctx->dev;
1434 const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1440 s5p_mfc_set_enc_params(ctx);
1500 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1502 struct s5p_mfc_dev *dev = ctx->dev;
1504 const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1511 s5p_mfc_set_enc_params(ctx);
1593 static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
1595 struct s5p_mfc_dev *dev = ctx->dev;
1597 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1604 s5p_mfc_set_enc_params(ctx);
1614 if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
1750 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1752 struct s5p_mfc_dev *dev = ctx->dev;
1758 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1768 if (ctx->display_delay_enable) {
1770 writel(ctx->display_delay, mfc_regs->d_display_delay);
1779 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1781 ctx->loop_filter_mpeg4);
1782 reg |= (ctx->loop_filter_mpeg4 <<
1785 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1794 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M)
1796 else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YVU420M)
1798 else if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1805 writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1807 writel(ctx->inst_no, mfc_regs->instance_id);
1815 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1817 struct s5p_mfc_dev *dev = ctx->dev;
1821 dev->curr_ctx = ctx->num;
1822 writel(ctx->inst_no, mfc_regs->instance_id);
1829 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1832 struct s5p_mfc_dev *dev = ctx->dev;
1835 writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1836 writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1838 writel(ctx->inst_no, mfc_regs->instance_id);
1859 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1861 struct s5p_mfc_dev *dev = ctx->dev;
1864 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1865 s5p_mfc_set_enc_params_h264(ctx);
1866 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1867 s5p_mfc_set_enc_params_mpeg4(ctx);
1868 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1869 s5p_mfc_set_enc_params_h263(ctx);
1870 else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1871 s5p_mfc_set_enc_params_vp8(ctx);
1872 else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
1873 s5p_mfc_set_enc_params_hevc(ctx);
1876 ctx->codec_mode);
1882 writel(ctx->stride[0], mfc_regs->e_source_first_plane_stride);
1883 writel(ctx->stride[1], mfc_regs->e_source_second_plane_stride);
1884 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
1886 writel(ctx->stride[2], mfc_regs->e_source_third_plane_stride);
1889 writel(ctx->inst_no, mfc_regs->instance_id);
1896 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1898 struct s5p_mfc_dev *dev = ctx->dev;
1900 const struct s5p_mfc_enc_params *p = &ctx->enc_params;
1914 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1916 struct s5p_mfc_dev *dev = ctx->dev;
1924 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1925 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1927 s5p_mfc_set_slice_mode(ctx);
1929 if (ctx->state != MFCINST_FINISHING)
1934 writel(ctx->inst_no, mfc_regs->instance_id);
1942 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1944 struct s5p_mfc_dev *dev = ctx->dev;
1946 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1947 dev->curr_ctx = ctx->num;
1948 s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);
1951 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1953 struct s5p_mfc_dev *dev = ctx->dev;
1957 if (ctx->state == MFCINST_FINISHING) {
1959 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1960 dev->curr_ctx = ctx->num;
1961 s5p_mfc_clean_ctx_int_flags(ctx);
1962 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1967 if (list_empty(&ctx->src_queue)) {
1972 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1974 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1976 ctx->consumed_stream,
1979 dev->curr_ctx = ctx->num;
1982 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1983 ctx->state = MFCINST_FINISHING;
1985 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1990 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1992 struct s5p_mfc_dev *dev = ctx->dev;
2001 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
2006 if (list_empty(&ctx->dst_queue)) {
2011 if (list_empty(&ctx->src_queue)) {
2013 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
2016 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
2019 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0, 0);
2020 ctx->state = MFCINST_FINISHING;
2024 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->src_fmt->fourcc ==
2034 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr, src_c_1_addr);
2036 ctx->state = MFCINST_FINISHING;
2040 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
2045 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
2047 dev->curr_ctx = ctx->num;
2048 s5p_mfc_encode_one_frame_v6(ctx);
2053 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
2055 struct s5p_mfc_dev *dev = ctx->dev;
2060 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
2062 s5p_mfc_set_dec_stream_buffer_v6(ctx,
2065 dev->curr_ctx = ctx->num;
2066 s5p_mfc_init_decode_v6(ctx);
2069 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
2071 struct s5p_mfc_dev *dev = ctx->dev;
2076 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
2079 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
2080 dev->curr_ctx = ctx->num;
2081 s5p_mfc_init_encode_v6(ctx);
2084 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
2086 struct s5p_mfc_dev *dev = ctx->dev;
2090 * s5p_mfc_alloc_dec_buffers(ctx); */
2092 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
2099 dev->curr_ctx = ctx->num;
2100 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
2103 ctx->state = MFCINST_ERROR;
2108 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
2110 struct s5p_mfc_dev *dev = ctx->dev;
2113 ret = s5p_mfc_hw_call(ctx->dev->mfc_ops, alloc_codec_buffers, ctx);
2120 dev->curr_ctx = ctx->num;
2121 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
2124 ctx->state = MFCINST_ERROR;
2132 struct s5p_mfc_ctx *ctx;
2140 /* This is perfectly ok, the scheduled ctx should wait */
2154 mfc_debug(1, "No ctx is scheduled to be run.\n");
2159 ctx = dev->ctx[new_ctx];
2160 mfc_debug(1, "Setting new context to %p\n", ctx);
2161 /* Got context to run in ctx */
2162 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
2163 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
2164 mfc_debug(1, "ctx->state=%d\n", ctx->state);
2169 s5p_mfc_clean_ctx_int_flags(ctx);
2171 if (ctx->type == MFCINST_DECODER) {
2172 switch (ctx->state) {
2174 s5p_mfc_run_dec_last_frames(ctx);
2177 ret = s5p_mfc_run_dec_frame(ctx);
2181 ctx);
2185 ctx);
2188 s5p_mfc_run_init_dec(ctx);
2191 ret = s5p_mfc_run_init_dec_buffers(ctx);
2194 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
2197 s5p_mfc_run_dec_last_frames(ctx);
2200 s5p_mfc_run_dec_last_frames(ctx);
2204 ctx->capture_state = QUEUE_FREE;
2206 s5p_mfc_run_init_dec(ctx);
2211 } else if (ctx->type == MFCINST_ENCODER) {
2212 switch (ctx->state) {
2215 ret = s5p_mfc_run_enc_frame(ctx);
2219 ctx);
2223 ctx);
2226 s5p_mfc_run_init_enc(ctx);
2229 ret = s5p_mfc_run_init_enc_buffers(ctx);
2235 mfc_err("invalid context type: %d\n", ctx->type);
2260 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)
2264 s5p_mfc_clock_on(ctx->dev);
2266 s5p_mfc_clock_off(ctx->dev);
2297 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
2299 struct s5p_mfc_dev *dev = ctx->dev;
2375 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2377 return s5p_mfc_read_info_v6(ctx,
2378 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2381 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2383 return s5p_mfc_read_info_v6(ctx,
2384 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2387 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2389 return s5p_mfc_read_info_v6(ctx,
2390 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);
2393 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2395 return s5p_mfc_read_info_v6(ctx,
2396 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);