Lines Matching refs:ctx
259 static int s5p_mfc_ctx_ready(struct s5p_mfc_ctx *ctx)
262 if (ctx->src_queue_cnt >= 1 && ctx->state == MFCINST_GOT_INST)
265 if (ctx->src_queue_cnt >= 1 &&
266 ctx->state == MFCINST_RUNNING &&
267 ctx->dst_queue_cnt >= ctx->pb_count)
270 if (ctx->state == MFCINST_FINISHING &&
271 ctx->dst_queue_cnt >= ctx->pb_count)
274 if (ctx->src_queue_cnt >= 1 &&
275 ctx->state == MFCINST_HEAD_PARSED &&
276 ctx->capture_state == QUEUE_BUFS_MMAPED)
279 if ((ctx->state == MFCINST_RES_CHANGE_INIT ||
280 ctx->state == MFCINST_RES_CHANGE_FLUSH) &&
281 ctx->dst_queue_cnt >= ctx->pb_count)
283 if (ctx->state == MFCINST_RES_CHANGE_END &&
284 ctx->src_queue_cnt >= 1)
286 mfc_debug(2, "ctx is not ready\n");
348 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
354 (ctx->state == MFCINST_GOT_INST || ctx->state ==
358 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_SEQ_DONE_RET,
362 ctx->state >= MFCINST_HEAD_PARSED &&
363 ctx->state < MFCINST_ABORT) {
369 pix_mp->width = ctx->buf_width;
370 pix_mp->height = ctx->buf_height;
372 pix_mp->num_planes = ctx->dst_fmt->num_planes;
375 pix_mp->pixelformat = ctx->dst_fmt->fourcc;
376 pix_mp->plane_fmt[0].bytesperline = ctx->stride[0];
377 pix_mp->plane_fmt[0].sizeimage = ctx->luma_size;
378 pix_mp->plane_fmt[1].bytesperline = ctx->stride[1];
379 pix_mp->plane_fmt[1].sizeimage = ctx->chroma_size;
380 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
382 pix_mp->plane_fmt[2].bytesperline = ctx->stride[2];
383 pix_mp->plane_fmt[2].sizeimage = ctx->chroma_size_1;
392 pix_mp->plane_fmt[0].bytesperline = ctx->dec_src_buf_size;
393 pix_mp->plane_fmt[0].sizeimage = ctx->dec_src_buf_size;
394 pix_mp->pixelformat = ctx->src_fmt->fourcc;
395 pix_mp->num_planes = ctx->src_fmt->num_planes;
445 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
455 if (vb2_is_streaming(&ctx->vq_src) || vb2_is_streaming(&ctx->vq_dst)) {
462 ctx->dst_fmt = find_format(f, MFC_FMT_RAW);
467 ctx->src_fmt = find_format(f, MFC_FMT_DEC);
468 ctx->codec_mode = ctx->src_fmt->codec_mode;
469 mfc_debug(2, "The codec number is: %d\n", ctx->codec_mode);
473 pix_mp->plane_fmt[0].sizeimage = ctx->dec_src_buf_size =
476 ctx->dec_src_buf_size = buf_size->cpb;
478 ctx->dec_src_buf_size = pix_mp->plane_fmt[0].sizeimage;
480 ctx->state = MFCINST_INIT;
494 static int reqbufs_output(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx,
503 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
506 ctx->src_bufs_cnt = 0;
507 ctx->output_state = QUEUE_FREE;
508 } else if (ctx->output_state == QUEUE_FREE) {
510 WARN_ON(ctx->src_bufs_cnt != 0);
511 if (ctx->state != MFCINST_INIT) {
519 ret = vb2_reqbufs(&ctx->vq_src, reqbufs);
523 ret = s5p_mfc_open_mfc_inst(dev, ctx);
526 vb2_reqbufs(&ctx->vq_src, reqbufs);
530 ctx->output_state = QUEUE_BUFS_REQUESTED;
542 static int reqbufs_capture(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx,
551 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
554 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
555 ctx->dst_bufs_cnt = 0;
556 } else if (ctx->capture_state == QUEUE_FREE) {
557 WARN_ON(ctx->dst_bufs_cnt != 0);
560 ret = vb2_reqbufs(&ctx->vq_dst, reqbufs);
564 ctx->capture_state = QUEUE_BUFS_REQUESTED;
565 ctx->total_dpb_count = reqbufs->count;
567 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_codec_buffers, ctx);
571 vb2_reqbufs(&ctx->vq_dst, reqbufs);
573 ctx->capture_state = QUEUE_FREE;
577 WARN_ON(ctx->dst_bufs_cnt != ctx->total_dpb_count);
578 ctx->capture_state = QUEUE_BUFS_MMAPED;
580 if (s5p_mfc_ctx_ready(ctx))
581 set_work_bit_irqsave(ctx);
583 s5p_mfc_wait_for_done_ctx(ctx, S5P_MFC_R2H_CMD_INIT_BUFFERS_RET,
601 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
609 return reqbufs_output(dev, ctx, reqbufs);
611 return reqbufs_capture(dev, ctx, reqbufs);
622 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
630 mfc_debug(2, "State: %d, buf->type: %d\n", ctx->state, buf->type);
631 if (ctx->state == MFCINST_GOT_INST &&
633 ret = vb2_querybuf(&ctx->vq_src, buf);
634 } else if (ctx->state == MFCINST_RUNNING &&
636 ret = vb2_querybuf(&ctx->vq_dst, buf);
650 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
652 if (ctx->state == MFCINST_ERROR) {
657 return vb2_qbuf(&ctx->vq_src, NULL, buf);
659 return vb2_qbuf(&ctx->vq_dst, NULL, buf);
669 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
672 if (ctx->state == MFCINST_ERROR) {
679 return vb2_dqbuf(&ctx->vq_src, buf, file->f_flags & O_NONBLOCK);
681 ret = vb2_dqbuf(&ctx->vq_dst, buf, file->f_flags & O_NONBLOCK);
685 if (ctx->state == MFCINST_FINISHED &&
686 (ctx->dst_bufs[buf->index].flags & MFC_BUF_FLAG_EOS))
687 v4l2_event_queue_fh(&ctx->fh, &ev);
698 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
701 return vb2_expbuf(&ctx->vq_src, eb);
703 return vb2_expbuf(&ctx->vq_dst, eb);
711 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
716 ret = vb2_streamon(&ctx->vq_src, type);
718 ret = vb2_streamon(&ctx->vq_dst, type);
727 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
730 return vb2_streamoff(&ctx->vq_src, type);
732 return vb2_streamoff(&ctx->vq_dst, type);
739 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
744 ctx->display_delay = ctrl->val;
748 ctx->display_delay_enable = ctrl->val;
751 ctx->loop_filter_mpeg4 = ctrl->val;
754 ctx->slice_interface = ctrl->val;
765 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl);
766 struct s5p_mfc_dev *dev = ctx->dev;
770 if (ctx->state >= MFCINST_HEAD_PARSED &&
771 ctx->state < MFCINST_ABORT) {
772 ctrl->val = ctx->pb_count;
774 } else if (ctx->state != MFCINST_INIT &&
775 ctx->state != MFCINST_RES_CHANGE_END) {
780 s5p_mfc_wait_for_done_ctx(ctx,
782 if (ctx->state >= MFCINST_HEAD_PARSED &&
783 ctx->state < MFCINST_ABORT) {
784 ctrl->val = ctx->pb_count;
804 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
805 struct s5p_mfc_dev *dev = ctx->dev;
812 if (ctx->state != MFCINST_HEAD_PARSED &&
813 ctx->state != MFCINST_RUNNING &&
814 ctx->state != MFCINST_FINISHING &&
815 ctx->state != MFCINST_FINISHED) {
819 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_H264) {
820 left = s5p_mfc_hw_call(dev->mfc_ops, get_crop_info_h, ctx);
823 top = s5p_mfc_hw_call(dev->mfc_ops, get_crop_info_v, ctx);
826 width = ctx->img_width - left - right;
827 height = ctx->img_height - top - bottom;
830 ctx->buf_width, ctx->buf_height);
834 width = ctx->img_width;
835 height = ctx->img_height;
837 s->r.width, s->r.height, ctx->buf_width,
838 ctx->buf_height);
859 struct s5p_mfc_ctx *ctx = fh_to_ctx(priv);
860 struct s5p_mfc_dev *dev = ctx->dev;
869 if (!vb2_is_streaming(&ctx->vq_src))
873 if (list_empty(&ctx->src_queue)) {
875 ctx->state = MFCINST_FINISHING;
876 if (s5p_mfc_ctx_ready(ctx))
877 set_work_bit_irqsave(ctx);
882 buf = list_entry(ctx->src_queue.prev,
885 ctx->state = MFCINST_FINISHING;
940 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
941 struct s5p_mfc_dev *dev = ctx->dev;
946 if (ctx->state == MFCINST_INIT &&
956 } else if (ctx->state == MFCINST_HEAD_PARSED &&
959 format = v4l2_format_info(ctx->dst_fmt->fourcc);
967 if (*buf_count < ctx->pb_count)
968 *buf_count = ctx->pb_count;
969 if (*buf_count > ctx->pb_count + MFC_MAX_EXTRA_DPB)
970 *buf_count = ctx->pb_count + MFC_MAX_EXTRA_DPB;
975 ctx->state, vq->type);
980 if (ctx->state == MFCINST_HEAD_PARSED &&
982 psize[0] = ctx->luma_size;
983 psize[1] = ctx->chroma_size;
984 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
986 psize[2] = ctx->chroma_size_1;
988 alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];
990 alloc_devs[0] = ctx->dev->mem_dev[BANK_R_CTX];
991 alloc_devs[1] = ctx->dev->mem_dev[BANK_L_CTX];
992 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
994 alloc_devs[2] = ctx->dev->mem_dev[BANK_L_CTX];
995 } else if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && ctx->state == MFCINST_INIT) {
996 psize[0] = ctx->dec_src_buf_size;
997 alloc_devs[0] = ctx->dev->mem_dev[BANK_L_CTX];
1009 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1013 if (ctx->capture_state == QUEUE_BUFS_MMAPED)
1015 for (i = 0; i < ctx->dst_fmt->num_planes; i++) {
1022 if (vb2_plane_size(vb, 0) < ctx->luma_size ||
1023 vb2_plane_size(vb, 1) < ctx->chroma_size) {
1027 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
1029 if (vb2_plane_size(vb, 2) < ctx->chroma_size_1) {
1035 ctx->dst_bufs[i].b = vbuf;
1036 ctx->dst_bufs[i].cookie.raw.luma =
1038 ctx->dst_bufs[i].cookie.raw.chroma =
1040 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_YUV420M || ctx->dst_fmt->fourcc ==
1042 ctx->dst_bufs[i].cookie.raw.chroma_1 =
1045 ctx->dst_bufs_cnt++;
1052 if (vb2_plane_size(vb, 0) < ctx->dec_src_buf_size) {
1058 ctx->src_bufs[i].b = vbuf;
1059 ctx->src_bufs[i].cookie.stream =
1061 ctx->src_bufs_cnt++;
1071 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1072 struct s5p_mfc_dev *dev = ctx->dev;
1074 v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
1075 if (ctx->state == MFCINST_FINISHING ||
1076 ctx->state == MFCINST_FINISHED)
1077 ctx->state = MFCINST_RUNNING;
1079 if (s5p_mfc_ctx_ready(ctx))
1080 set_work_bit_irqsave(ctx);
1088 struct s5p_mfc_ctx *ctx = fh_to_ctx(q->drv_priv);
1089 struct s5p_mfc_dev *dev = ctx->dev;
1093 if ((ctx->state == MFCINST_FINISHING ||
1094 ctx->state == MFCINST_RUNNING) &&
1095 dev->curr_ctx == ctx->num && dev->hw_lock) {
1096 ctx->state = MFCINST_ABORT;
1098 s5p_mfc_wait_for_done_ctx(ctx,
1104 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
1105 INIT_LIST_HEAD(&ctx->dst_queue);
1106 ctx->dst_queue_cnt = 0;
1107 ctx->dpb_flush_flag = 1;
1108 ctx->dec_dst_flag = 0;
1109 if (IS_MFCV6_PLUS(dev) && (ctx->state == MFCINST_RUNNING)) {
1110 ctx->state = MFCINST_FLUSH;
1111 set_work_bit_irqsave(ctx);
1114 if (s5p_mfc_wait_for_done_ctx(ctx,
1120 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
1121 INIT_LIST_HEAD(&ctx->src_queue);
1122 ctx->src_queue_cnt = 0;
1125 ctx->state = MFCINST_RUNNING;
1133 struct s5p_mfc_ctx *ctx = fh_to_ctx(vq->drv_priv);
1134 struct s5p_mfc_dev *dev = ctx->dev;
1139 mfc_buf = &ctx->src_bufs[vb->index];
1142 list_add_tail(&mfc_buf->list, &ctx->src_queue);
1143 ctx->src_queue_cnt++;
1146 mfc_buf = &ctx->dst_bufs[vb->index];
1150 set_bit(vb->index, &ctx->dec_dst_flag);
1151 list_add_tail(&mfc_buf->list, &ctx->dst_queue);
1152 ctx->dst_queue_cnt++;
1157 if (s5p_mfc_ctx_ready(ctx))
1158 set_work_bit_irqsave(ctx);
1190 int s5p_mfc_dec_ctrls_setup(struct s5p_mfc_ctx *ctx)
1195 v4l2_ctrl_handler_init(&ctx->ctrl_handler, NUM_CTRLS);
1196 if (ctx->ctrl_handler.error) {
1198 return ctx->ctrl_handler.error;
1215 ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->ctrl_handler,
1218 ctx->ctrls[i] = v4l2_ctrl_new_std(&ctx->ctrl_handler,
1224 if (ctx->ctrl_handler.error) {
1226 return ctx->ctrl_handler.error;
1228 if (controls[i].is_volatile && ctx->ctrls[i])
1229 ctx->ctrls[i]->flags |= V4L2_CTRL_FLAG_VOLATILE;
1234 void s5p_mfc_dec_ctrls_delete(struct s5p_mfc_ctx *ctx)
1238 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
1240 ctx->ctrls[i] = NULL;
1243 void s5p_mfc_dec_init(struct s5p_mfc_ctx *ctx)
1247 ctx->src_fmt = find_format(&f, MFC_FMT_DEC);
1248 if (IS_MFCV8_PLUS(ctx->dev))
1250 else if (IS_MFCV6_PLUS(ctx->dev))
1254 ctx->dst_fmt = find_format(&f, MFC_FMT_RAW);
1256 ctx->src_fmt, ctx->dst_fmt);