Lines Matching refs:dev
23 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
25 struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
28 fw_buf->size = dev->variant->buf_size->fw;
35 err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
45 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
59 if (!IS_MFCV12(dev))
60 if (dev->fw_get_done)
64 if (!dev->variant->fw_name[i])
67 dev->variant->fw_name[i], &dev->plat_dev->dev);
69 dev->fw_ver = (enum s5p_mfc_fw_ver) i;
78 if (fw_blob->size > dev->fw_buf.size) {
83 memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
85 dev->fw_get_done = true;
92 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
96 s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
97 dev->fw_get_done = false;
101 static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
107 mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
115 status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
121 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
129 if (IS_MFCV6_PLUS(dev)) {
131 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
132 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
133 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
136 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
139 if (dev->risc_on && !IS_MFCV12(dev))
140 if (s5p_mfc_bus_reset(dev))
146 if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
147 mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
149 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
150 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
154 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
156 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
167 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
171 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
172 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
179 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
181 if (IS_MFCV6_PLUS(dev)) {
182 mfc_write(dev, dev->dma_base[BANK_L_CTX],
185 &dev->dma_base[BANK_L_CTX]);
187 mfc_write(dev, dev->dma_base[BANK_L_CTX],
189 mfc_write(dev, dev->dma_base[BANK_R_CTX],
192 &dev->dma_base[BANK_L_CTX],
193 &dev->dma_base[BANK_R_CTX]);
197 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
199 if (IS_MFCV6_PLUS(dev)) {
203 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
204 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
205 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
206 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
211 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
217 if (!dev->fw_buf.virt) {
224 s5p_mfc_clock_on(dev);
225 dev->risc_on = 0;
226 ret = s5p_mfc_reset(dev);
233 s5p_mfc_init_memctrl(dev);
235 s5p_mfc_clear_cmds(dev);
237 s5p_mfc_clean_dev_int_flags(dev);
238 if (IS_MFCV6_PLUS(dev)) {
239 dev->risc_on = 1;
240 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
243 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
245 if (IS_MFCV10_PLUS(dev))
246 mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
249 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
251 s5p_mfc_reset(dev);
252 s5p_mfc_clock_off(dev);
255 s5p_mfc_clean_dev_int_flags(dev);
257 ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
260 s5p_mfc_reset(dev);
261 s5p_mfc_clock_off(dev);
265 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
267 s5p_mfc_reset(dev);
268 s5p_mfc_clock_off(dev);
271 dev->int_cond = 0;
272 if (dev->int_err != 0 || dev->int_type !=
276 dev->int_err, dev->int_type);
277 s5p_mfc_reset(dev);
278 s5p_mfc_clock_off(dev);
281 if (IS_MFCV6_PLUS(dev))
282 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
284 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
288 s5p_mfc_clock_off(dev);
295 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
297 s5p_mfc_clock_on(dev);
299 s5p_mfc_reset(dev);
300 s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
302 s5p_mfc_clock_off(dev);
305 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
310 s5p_mfc_clock_on(dev);
311 s5p_mfc_clean_dev_int_flags(dev);
312 ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
317 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
321 s5p_mfc_clock_off(dev);
322 dev->int_cond = 0;
323 if (dev->int_err != 0 || dev->int_type !=
326 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
327 dev->int_type);
334 static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
339 dev->risc_on = 1;
340 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
342 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
347 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
353 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
360 static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
365 ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
372 if (IS_MFCV6_PLUS(dev)) {
373 dev->risc_on = 1;
374 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
376 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
379 if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
386 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
393 s5p_mfc_clock_on(dev);
394 dev->risc_on = 0;
395 ret = s5p_mfc_reset(dev);
398 s5p_mfc_clock_off(dev);
403 s5p_mfc_init_memctrl(dev);
405 s5p_mfc_clear_cmds(dev);
406 s5p_mfc_clean_dev_int_flags(dev);
408 if (IS_MFCV8_PLUS(dev))
409 ret = s5p_mfc_v8_wait_wakeup(dev);
411 ret = s5p_mfc_wait_wakeup(dev);
413 s5p_mfc_clock_off(dev);
417 dev->int_cond = 0;
418 if (dev->int_err != 0 || dev->int_type !=
421 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
422 dev->int_type);
429 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
433 ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
440 ret = s5p_mfc_hw_call(dev->mfc_ops,
449 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
463 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
465 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
470 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
474 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
483 s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
484 s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
486 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);