samsung/exynos4-is/fimc-lite-reg.c

25 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
27 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
30 		cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
37 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
42 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS);
44 	writel(cfg, dev->regs + FLITE_REG_CISTATUS);
49 	u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS);
56 	u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2);
58 	writel(cfg, dev->regs + FLITE_REG_CISTATUS2);
77 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
80 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
85 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
87 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
92 	u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT);
94 	writel(cfg, dev->regs + FLITE_REG_CIIMGCPT);
103 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
108 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
144 	cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
147 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
149 	cfg = readl(dev->regs + FLITE_REG_CISRCSIZE);
154 	writel(cfg, dev->regs + FLITE_REG_CISRCSIZE);
163 	cfg = readl(dev->regs + FLITE_REG_CIWDOFST);
167 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST);
173 	writel(cfg, dev->regs + FLITE_REG_CIWDOFST2);
179 	u32 cfg = readl(dev->regs + FLITE_REG_CIGENERAL);
184 	writel(cfg, dev->regs + FLITE_REG_CIGENERAL);
191 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
212 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
219 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
226 	writel(cfg, dev->regs + FLITE_REG_CIODMAFMT);
238 	u32 cfg = readl(dev->regs + FLITE_REG_CIODMAFMT);
245 	writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT);
253 	cfg = readl(dev->regs + FLITE_REG_CIOCAN);
256 	writel(cfg, dev->regs + FLITE_REG_CIOCAN);
259 	cfg = readl(dev->regs + FLITE_REG_CIOOFF);
262 	writel(cfg, dev->regs + FLITE_REG_CIOOFF);
276 		writel(buf->addr, dev->regs + FLITE_REG_CIOSA);
278 		writel(buf->addr, dev->regs + FLITE_REG_CIOSAN(index - 1));
280 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
282 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
292 	cfg = readl(dev->regs + FLITE_REG_CIFCNTSEQ);
294 	writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ);
301 	u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL);
305 		writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
310 	writel(cfg, dev->regs + FLITE_REG_CIGCTRL);
343 		u32 cfg = readl(dev->regs + registers[i].offset);