Lines Matching refs:is
33 #include "fimc-is.h"
34 #include "fimc-is-command.h"
35 #include "fimc-is-errno.h"
36 #include "fimc-is-i2c.h"
37 #include "fimc-is-param.h"
38 #include "fimc-is-regs.h"
65 static void fimc_is_put_clocks(struct fimc_is *is)
70 if (IS_ERR(is->clocks[i]))
72 clk_put(is->clocks[i]);
73 is->clocks[i] = ERR_PTR(-EINVAL);
77 static int fimc_is_get_clocks(struct fimc_is *is)
82 is->clocks[i] = ERR_PTR(-EINVAL);
85 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
86 if (IS_ERR(is->clocks[i])) {
87 ret = PTR_ERR(is->clocks[i]);
94 fimc_is_put_clocks(is);
95 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
100 static int fimc_is_setup_clocks(struct fimc_is *is)
104 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
105 is->clocks[ISS_CLK_ACLK200_DIV]);
109 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
110 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
114 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
118 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
122 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
127 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
131 static int fimc_is_enable_clocks(struct fimc_is *is)
136 if (IS_ERR(is->clocks[i]))
138 ret = clk_prepare_enable(is->clocks[i]);
140 dev_err(&is->pdev->dev, "clock %s enable failed\n",
143 clk_disable_unprepare(is->clocks[i]);
151 static void fimc_is_disable_clocks(struct fimc_is *is)
156 if (!IS_ERR(is->clocks[i])) {
157 clk_disable_unprepare(is->clocks[i]);
163 static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
166 struct fimc_is_sensor *sensor = &is->sensor[index];
173 dev_err(&is->pdev->dev, "no driver data found for: %pOF\n",
190 dev_err(&is->pdev->dev, "reg property not found at: %pOF\n",
201 static int fimc_is_register_subdevs(struct fimc_is *is)
206 ret = fimc_isp_subdev_create(&is->isp);
212 ret = fimc_is_parse_sensor_config(is, index, child);
225 static int fimc_is_unregister_subdevs(struct fimc_is *is)
227 fimc_isp_subdev_destroy(&is->isp);
231 static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
237 ret = request_firmware(&fw, file_name, &is->pdev->dev);
239 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
242 buf = is->memory.vaddr + is->setfile.base;
245 is->setfile.size = fw->size;
247 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
249 memcpy(is->fw.setfile_info,
253 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
254 is->setfile.state = 1;
257 is->setfile.base, fw->size);
263 int fimc_is_cpu_set_power(struct fimc_is *is, int on)
269 mcuctl_write(0, is, REG_WDT_ISP);
272 mcuctl_write(is->memory.addr, is, MCUCTL_REG_BBOAR);
275 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
276 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
279 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
280 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
282 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
293 /* Wait until @bit of @is->state is set to @state in the interrupt handler. */
294 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
298 int ret = wait_event_timeout(is->irq_queue,
299 !state ^ test_bit(bit, &is->state),
302 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
308 int fimc_is_start_firmware(struct fimc_is *is)
310 struct device *dev = &is->pdev->dev;
313 if (is->fw.f_w == NULL) {
314 dev_err(dev, "firmware is not loaded\n");
318 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
321 ret = fimc_is_cpu_set_power(is, 1);
325 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
334 static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
336 struct device *dev = &is->pdev->dev;
338 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
339 &is->memory.addr, GFP_KERNEL);
340 if (is->memory.vaddr == NULL)
343 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
345 dev_info(dev, "FIMC-IS CPU memory base: %pad\n", &is->memory.addr);
347 if (((u32)is->memory.addr) & FIMC_IS_FW_ADDR_MASK) {
349 (u32)is->memory.addr);
350 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
351 is->memory.addr);
355 is->is_p_region = (struct is_region *)(is->memory.vaddr +
358 is->is_dma_p_region = is->memory.addr +
361 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
366 static void fimc_is_free_cpu_memory(struct fimc_is *is)
368 struct device *dev = &is->pdev->dev;
370 if (is->memory.vaddr == NULL)
373 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
374 is->memory.addr);
379 struct fimc_is *is = context;
380 struct device *dev = &is->pdev->dev;
388 mutex_lock(&is->lock);
395 is->fw.size = fw->size;
397 ret = fimc_is_alloc_cpu_memory(is);
403 memcpy(is->memory.vaddr, fw->data, fw->size);
407 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
408 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
409 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
411 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
412 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
413 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
415 is->fw.state = 1;
418 is->fw.info, is->fw.version);
419 dev_dbg(dev, "FW size: %zu, DMA addr: %pad\n", fw->size, &is->memory.addr);
421 is->is_shared_region->chip_id = 0xe4412;
422 is->is_shared_region->chip_rev_no = 1;
427 * FIXME: The firmware is not being released for now, as it is
429 * time before the Cortex-A5 is restarted.
431 release_firmware(is->fw.f_w);
432 is->fw.f_w = fw;
434 mutex_unlock(&is->lock);
437 static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
440 FW_ACTION_UEVENT, fw_name, &is->pdev->dev,
441 GFP_KERNEL, is, fimc_is_load_firmware);
445 static void fimc_is_general_irq_handler(struct fimc_is *is)
447 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
449 switch (is->i2h_cmd.cmd) {
451 fimc_is_hw_get_params(is, 1);
452 fimc_is_hw_wait_intmsr0_intmsd0(is);
453 fimc_is_hw_set_sensor_num(is);
454 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
458 fimc_is_hw_get_params(is, 2);
463 fimc_is_hw_get_params(is, 3);
466 fimc_is_hw_get_params(is, 4);
471 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
474 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
476 switch (is->i2h_cmd.cmd) {
478 fimc_is_hw_set_intgr0_gd0(is);
479 set_bit(IS_ST_A5_PWR_ON, &is->state);
486 is->fd_header.count = is->i2h_cmd.args[0];
487 is->fd_header.index = is->i2h_cmd.args[1];
488 is->fd_header.offset = 0;
495 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
496 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
500 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
502 switch (is->i2h_cmd.args[0]) {
505 set_bit(IS_ST_CHANGE_MODE, &is->state);
506 is->isp.cac_margin_x = is->i2h_cmd.args[1];
507 is->isp.cac_margin_y = is->i2h_cmd.args[2];
509 is->isp.cac_margin_x, is->isp.cac_margin_y);
513 clear_bit(IS_ST_STREAM_OFF, &is->state);
514 set_bit(IS_ST_STREAM_ON, &is->state);
518 clear_bit(IS_ST_STREAM_ON, &is->state);
519 set_bit(IS_ST_STREAM_OFF, &is->state);
523 is->config[is->config_index].p_region_index[0] = 0;
524 is->config[is->config_index].p_region_index[1] = 0;
525 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
539 set_bit(IS_ST_OPEN_SENSOR, &is->state);
541 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
545 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
546 is->sensor_index = 0;
554 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
558 is->setfile.base = is->i2h_cmd.args[1];
559 set_bit(IS_ST_SETFILE_LOADED, &is->state);
563 set_bit(IS_ST_SETFILE_LOADED, &is->state);
569 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
570 is->i2h_cmd.args[1],
571 fimc_is_strerr(is->i2h_cmd.args[1]));
573 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
576 switch (is->i2h_cmd.args[1]) {
581 switch (is->i2h_cmd.args[0]) {
583 is->config[is->config_index].p_region_index[0] = 0;
584 is->config[is->config_index].p_region_index[1] = 0;
585 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
595 wake_up(&is->irq_queue);
600 struct fimc_is *is = priv;
604 spin_lock_irqsave(&is->slock, flags);
605 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
608 fimc_is_general_irq_handler(is);
611 fimc_isp_irq_handler(is);
613 spin_unlock_irqrestore(&is->slock, flags);
617 static int fimc_is_hw_open_sensor(struct fimc_is *is,
620 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
622 fimc_is_hw_wait_intmsr0_intmsd0(is);
640 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
641 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
642 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
643 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
644 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
646 fimc_is_hw_set_intgr0_gd0(is);
648 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
653 int fimc_is_hw_initialize(struct fimc_is *is)
659 struct device *dev = &is->pdev->dev;
663 /* Sensor initialization. Only one sensor is currently supported. */
664 ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
669 fimc_is_hw_get_setfile_addr(is);
671 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
677 pr_debug("setfile.base: %#x\n", is->setfile.base);
680 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
681 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
682 fimc_is_hw_load_setfile(is);
683 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
691 is->setfile.base, is->setfile.size);
692 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
695 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
702 &is->memory.addr + FIMC_IS_SHARED_REGION_OFFSET,
703 &is->is_dma_p_region);
705 is->setfile.sub_index = 0;
708 fimc_is_hw_stream_off(is);
709 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
717 prev_id = is->config_index;
721 is->config_index = config_ids[i];
722 fimc_is_set_initial_params(is);
723 ret = fimc_is_itf_s_param(is, true);
725 is->config_index = prev_id;
729 is->config_index = prev_id;
731 set_bit(IS_ST_INIT_DONE, &is->state);
733 is->config_index);
739 struct fimc_is *is = s->private;
740 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
742 if (is->memory.vaddr == NULL) {
743 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
753 static void fimc_is_debugfs_remove(struct fimc_is *is)
755 debugfs_remove_recursive(is->debugfs_entry);
756 is->debugfs_entry = NULL;
759 static void fimc_is_debugfs_create(struct fimc_is *is)
761 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
763 debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry, is,
794 struct fimc_is *is;
798 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
799 if (!is)
802 is->pdev = pdev;
803 is->isp.pdev = pdev;
805 init_waitqueue_head(&is->irq_queue);
806 spin_lock_init(&is->slock);
807 mutex_init(&is->lock);
813 is->regs = devm_ioremap_resource(dev, &res);
814 if (IS_ERR(is->regs))
815 return PTR_ERR(is->regs);
817 is->pmu_regs = fimc_is_get_pmu_regs(dev);
818 if (IS_ERR(is->pmu_regs))
819 return PTR_ERR(is->pmu_regs);
821 is->irq = irq_of_parse_and_map(dev->of_node, 0);
822 if (!is->irq) {
828 ret = fimc_is_get_clocks(is);
832 platform_set_drvdata(pdev, is);
834 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
861 ret = fimc_is_register_subdevs(is);
865 fimc_is_debugfs_create(is);
867 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
877 fimc_is_debugfs_remove(is);
878 fimc_is_unregister_subdevs(is);
886 free_irq(is->irq, is);
888 fimc_is_put_clocks(is);
890 iounmap(is->pmu_regs);
896 struct fimc_is *is = dev_get_drvdata(dev);
899 ret = fimc_is_setup_clocks(is);
903 return fimc_is_enable_clocks(is);
908 struct fimc_is *is = dev_get_drvdata(dev);
910 fimc_is_disable_clocks(is);
923 struct fimc_is *is = dev_get_drvdata(dev);
926 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
936 struct fimc_is *is = dev_get_drvdata(dev);
942 free_irq(is->irq, is);
943 fimc_is_unregister_subdevs(is);
945 fimc_is_put_clocks(is);
946 iounmap(is->pmu_regs);
947 fimc_is_debugfs_remove(is);
948 release_firmware(is->fw.f_w);
949 fimc_is_free_cpu_memory(is);
953 { .compatible = "samsung,exynos4212-fimc-is" },