samsung/exynos4-is/fimc-is-regs.c

12 #include "fimc-is.h"
13 #include "fimc-is-command.h"
14 #include "fimc-is-regs.h"
15 #include "fimc-is-sensor.h"
17 void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr)
19 	mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1);
22 void fimc_is_fw_clear_irq2(struct fimc_is *is)
24 	u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2);
25 	mcuctl_write(cfg, is, MCUCTL_REG_INTCR2);
28 void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is)
30 	mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0);
33 int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is)
39 		cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0);
43 			dev_warn(&is->pdev->dev, "%s timeout\n",
53 int fimc_is_hw_set_param(struct fimc_is *is)
55 	struct chain_config *config = &is->config[is->config_index];
56 	unsigned int param_count = __get_pending_param_count(is);
58 	fimc_is_hw_wait_intmsr0_intmsd0(is);
60 	mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0));
61 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
62 	mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2));
64 	mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3));
65 	mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4));
66 	mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5));
68 	fimc_is_hw_set_intgr0_gd0(is);
72 static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is)
74 	fimc_is_hw_wait_intmsr0_intmsd0(is);
76 	mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0));
77 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
78 	mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2));
80 	fimc_is_hw_set_intgr0_gd0(is);
86 int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args)
93 	is->i2h_cmd.num_args = num_args;
97 			is->i2h_cmd.args[i] = mcuctl_read(is,
100 			is->i2h_cmd.args[i] = 0;
105 void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask)
108 		dev_err(&is->pdev->dev, "%s(): not enough buffers (mask %#x)\n",
113 	if (mcuctl_read(is, MCUCTL_REG_ISSR(23)) != 0)
114 		dev_dbg(&is->pdev->dev, "non-zero DMA buffer mask\n");
116 	mcuctl_write(mask, is, MCUCTL_REG_ISSR(23));
119 void fimc_is_hw_set_sensor_num(struct fimc_is *is)
121 	pr_debug("setting sensor index to: %d\n", is->sensor_index);
123 	mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0));
124 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
125 	mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2));
126 	mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3));
129 void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index)
131 	if (is->sensor_index != index)
134 	fimc_is_hw_wait_intmsr0_intmsd0(is);
135 	mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0));
136 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
137 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2));
138 	fimc_is_hw_set_intgr0_gd0(is);
141 void fimc_is_hw_get_setfile_addr(struct fimc_is *is)
143 	fimc_is_hw_wait_intmsr0_intmsd0(is);
144 	mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0));
145 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
146 	fimc_is_hw_set_intgr0_gd0(is);
149 void fimc_is_hw_load_setfile(struct fimc_is *is)
151 	fimc_is_hw_wait_intmsr0_intmsd0(is);
152 	mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0));
153 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
154 	fimc_is_hw_set_intgr0_gd0(is);
157 int fimc_is_hw_change_mode(struct fimc_is *is)
164 	if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd)))
167 	mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0));
168 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
169 	mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2));
170 	fimc_is_hw_set_intgr0_gd0(is);
174 void fimc_is_hw_stream_on(struct fimc_is *is)
176 	fimc_is_hw_wait_intmsr0_intmsd0(is);
177 	mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0));
178 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
179 	mcuctl_write(0, is, MCUCTL_REG_ISSR(2));
180 	fimc_is_hw_set_intgr0_gd0(is);
183 void fimc_is_hw_stream_off(struct fimc_is *is)
185 	fimc_is_hw_wait_intmsr0_intmsd0(is);
186 	mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0));
187 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
188 	fimc_is_hw_set_intgr0_gd0(is);
191 void fimc_is_hw_subip_power_off(struct fimc_is *is)
193 	fimc_is_hw_wait_intmsr0_intmsd0(is);
194 	mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0));
195 	mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
196 	fimc_is_hw_set_intgr0_gd0(is);
199 int fimc_is_itf_s_param(struct fimc_is *is, bool update)
204 		__is_hw_update_params(is);
208 	clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
209 	fimc_is_hw_set_param(is);
210 	ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1,
213 		dev_err(&is->pdev->dev, "%s() timeout\n", __func__);
218 int fimc_is_itf_mode_change(struct fimc_is *is)
222 	clear_bit(IS_ST_CHANGE_MODE, &is->state);
223 	fimc_is_hw_change_mode(is);
224 	ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1,
227 		dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n",
228 			__func__, is->config_index);