renesas/vsp1/vsp1_drm.c

33 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
36 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
64 			      struct vsp1_pipeline *pipe,
116 				      struct vsp1_pipeline *pipe,
190 	ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
191 				 pipe->brx, brx_input);
198 	ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
205 		format.format.code, BRX_NAME(pipe->brx), format.pad);
211 	ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
218 		BRX_NAME(pipe->brx), sel.pad);
225 					 struct vsp1_pipeline *pipe);
226 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
229 				      struct vsp1_pipeline *pipe)
231 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
244 	if (pipe->num_inputs > 2)
246 	else if (pipe->brx && !drm_pipe->force_brx_release)
247 		brx = pipe->brx;
248 	else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe)
254 	if (brx != pipe->brx) {
258 		if (pipe->brx) {
259 			dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
260 				__func__, pipe->lif->index,
261 				BRX_NAME(pipe->brx));
277 			released_brx = pipe->brx;
279 			list_del(&pipe->brx->list_pipe);
280 			pipe->brx->sink = NULL;
281 			pipe->brx->pipe = NULL;
282 			pipe->brx = NULL;
289 		if (brx->pipe) {
292 			dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
293 				__func__, pipe->lif->index, BRX_NAME(brx));
295 			owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
298 			vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
299 			vsp1_du_pipeline_configure(&owner_pipe->pipe);
307 					 owner_pipe->pipe.lif->index);
313 		 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
316 		if (released_brx && !released_brx->pipe)
318 				      &pipe->entities);
321 		dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
322 			__func__, pipe->lif->index, BRX_NAME(brx));
324 		pipe->brx = brx;
325 		pipe->brx->pipe = pipe;
326 		pipe->brx->sink = &pipe->output->entity;
327 		pipe->brx->sink_pad = 0;
329 		list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
368 					struct vsp1_pipeline *pipe)
370 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
379 	pipe->num_inputs = 0;
385 		if (!pipe->inputs[i])
389 		for (j = pipe->num_inputs++; j > 0; --j) {
403 	ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
406 			BRX_NAME(pipe->brx));
410 	brx = to_brx(&pipe->brx->subdev);
413 	for (i = 0; i < pipe->brx->source_pad; ++i) {
421 		if (!rpf->entity.pipe) {
422 			rpf->entity.pipe = pipe;
423 			list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
428 		rpf->entity.sink = pipe->brx;
432 			__func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
438 		ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
451 	ret = vsp1_du_insert_uif(vsp1, pipe, uif,
452 				 pipe->brx, pipe->brx->source_pad,
453 				 &pipe->output->entity, 0);
456 			__func__, BRX_NAME(pipe->brx));
458 	/* If the DRM pipe does not have a UIF there is nothing we can update. */
463 	 * If the UIF is not in use schedule it for removal by setting its pipe
470 		drm_pipe->uif->pipe = NULL;
471 	} else if (!drm_pipe->uif->pipe) {
472 		drm_pipe->uif->pipe = pipe;
473 		list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
481 					 struct vsp1_pipeline *pipe)
483 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
495 	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
502 		format.format.code, pipe->output->entity.index);
505 	ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
512 		format.format.code, pipe->output->entity.index);
515 	ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
522 		format.format.code, pipe->lif->index);
532 			pipe->lif->index);
540 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
542 	struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
551 	if (pipe->output->writeback)
554 	dl = vsp1_dl_list_get(pipe->output->dlm);
557 	list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
559 		if (!entity->pipe) {
569 		vsp1_entity_route_setup(entity, pipe, dlb);
570 		vsp1_entity_configure_stream(entity, pipe, dl, dlb);
571 		vsp1_entity_configure_frame(entity, pipe, dl, dlb);
572 		vsp1_entity_configure_partition(entity, pipe, dl, dlb);
649 	struct vsp1_pipeline *pipe;
657 	drm_pipe = &vsp1->drm->pipe[pipe_index];
658 	pipe = &drm_pipe->pipe;
665 		brx = to_brx(&pipe->brx->subdev);
671 		ret = vsp1_pipeline_stop(pipe);
675 		for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
676 			struct vsp1_rwpf *rpf = pipe->inputs[i];
682 			 * Remove the RPF from the pipe and the list of BRx
685 			WARN_ON(!rpf->entity.pipe);
686 			rpf->entity.pipe = NULL;
688 			pipe->inputs[i] = NULL;
694 		pipe->num_inputs = 0;
696 		dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
697 			__func__, pipe->lif->index,
698 			BRX_NAME(pipe->brx));
700 		list_del(&pipe->brx->list_pipe);
701 		pipe->brx->pipe = NULL;
702 		pipe->brx = NULL;
706 		vsp1_dlm_reset(pipe->output->dlm);
715 	pipe->underrun_count = 0;
719 	pipe->interlaced = cfg->interlaced;
723 		pipe->interlaced ? "i" : "");
728 	ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
732 	ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
753 	vsp1_du_pipeline_configure(pipe);
762 	spin_lock_irqsave(&pipe->irqlock, flags);
763 	vsp1_pipeline_run(pipe);
764 	spin_unlock_irqrestore(&pipe->irqlock, flags);
817 	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
835 		rpf->entity.pipe = NULL;
836 		drm_pipe->pipe.inputs[rpf_index] = NULL;
869 	drm_pipe->pipe.inputs[rpf_index] = rpf;
879  * @cfg: atomic pipe configuration
885 	struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
886 	struct vsp1_pipeline *pipe = &drm_pipe->pipe;
896 		ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output,
902 		pipe->output->mem.addr[0] = wb_cfg->mem[0];
903 		pipe->output->mem.addr[1] = wb_cfg->mem[1];
904 		pipe->output->mem.addr[2] = wb_cfg->mem[2];
905 		pipe->output->writeback = true;
908 	vsp1_du_pipeline_setup_inputs(vsp1, pipe);
909 	vsp1_du_pipeline_configure(pipe);
955 		struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
956 		struct vsp1_pipeline *pipe = &drm_pipe->pipe;
960 		vsp1_pipeline_init(pipe);
962 		pipe->frame_end = vsp1_du_pipeline_frame_end;
968 		pipe->output = vsp1->wpf[i];
969 		pipe->lif = &vsp1->lif[i]->entity;
971 		pipe->output->entity.pipe = pipe;
972 		pipe->output->entity.sink = pipe->lif;
973 		pipe->output->entity.sink_pad = 0;
974 		list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
976 		pipe->lif->pipe = pipe;
977 		list_add_tail(&pipe->lif->list_pipe, &pipe->entities);