Lines Matching defs:fdp1
57 #define dprintk(fdp1, fmt, arg...) \
58 v4l2_dbg(1, debug, &fdp1->v4l2_dev, "%s: " fmt, __func__, ## arg)
277 * @fmt: 7-bit format code for the fdp1 hardware
581 struct fdp1_dev *fdp1;
652 static struct fdp1_job *list_remove_job(struct fdp1_dev *fdp1,
658 spin_lock_irqsave(&fdp1->irqlock, flags);
662 spin_unlock_irqrestore(&fdp1->irqlock, flags);
672 static void list_add_job(struct fdp1_dev *fdp1,
678 spin_lock_irqsave(&fdp1->irqlock, flags);
680 spin_unlock_irqrestore(&fdp1->irqlock, flags);
683 static struct fdp1_job *fdp1_job_alloc(struct fdp1_dev *fdp1)
685 return list_remove_job(fdp1, &fdp1->free_job_list);
688 static void fdp1_job_free(struct fdp1_dev *fdp1, struct fdp1_job *job)
693 list_add_job(fdp1, &fdp1->free_job_list, job);
696 static void queue_job(struct fdp1_dev *fdp1, struct fdp1_job *job)
698 list_add_job(fdp1, &fdp1->queued_job_list, job);
701 static struct fdp1_job *get_queued_job(struct fdp1_dev *fdp1)
703 return list_remove_job(fdp1, &fdp1->queued_job_list);
706 static void queue_hw_job(struct fdp1_dev *fdp1, struct fdp1_job *job)
708 list_add_job(fdp1, &fdp1->hw_job_list, job);
711 static struct fdp1_job *get_hw_queued_job(struct fdp1_dev *fdp1)
713 return list_remove_job(fdp1, &fdp1->hw_job_list);
735 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
737 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
749 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
754 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
768 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
771 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
776 static u32 fdp1_read(struct fdp1_dev *fdp1, unsigned int reg)
778 u32 value = ioread32(fdp1->regs + reg);
781 dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg);
786 static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg)
789 dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg);
791 iowrite32(val, fdp1->regs + reg);
797 struct fdp1_dev *fdp1 = ctx->fdp1;
799 fdp1_write(fdp1, FD1_IPC_SMSK_THRESH_CONST, FD1_IPC_SMSK_THRESH);
800 fdp1_write(fdp1, FD1_IPC_COMB_DET_CONST, FD1_IPC_COMB_DET);
801 fdp1_write(fdp1, FD1_IPC_MOTDEC_CONST, FD1_IPC_MOTDEC);
803 fdp1_write(fdp1, FD1_IPC_DLI_BLEND_CONST, FD1_IPC_DLI_BLEND);
804 fdp1_write(fdp1, FD1_IPC_DLI_HGAIN_CONST, FD1_IPC_DLI_HGAIN);
805 fdp1_write(fdp1, FD1_IPC_DLI_SPRS_CONST, FD1_IPC_DLI_SPRS);
806 fdp1_write(fdp1, FD1_IPC_DLI_ANGLE_CONST, FD1_IPC_DLI_ANGLE);
807 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX0_CONST, FD1_IPC_DLI_ISOPIX0);
808 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX1_CONST, FD1_IPC_DLI_ISOPIX1);
814 struct fdp1_dev *fdp1 = ctx->fdp1;
823 fdp1_write(fdp1, FD1_IPC_SENSOR_TH0_CONST, FD1_IPC_SENSOR_TH0);
824 fdp1_write(fdp1, FD1_IPC_SENSOR_TH1_CONST, FD1_IPC_SENSOR_TH1);
825 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL0_CONST, FD1_IPC_SENSOR_CTL0);
826 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL1_CONST, FD1_IPC_SENSOR_CTL1);
828 fdp1_write(fdp1, ((hsize - 1) << FD1_IPC_SENSOR_CTL2_X_SHIFT) |
832 fdp1_write(fdp1, (x0 << FD1_IPC_SENSOR_CTL3_0_SHIFT) |
846 static void fdp1_write_lut(struct fdp1_dev *fdp1, const u8 *lut,
856 fdp1_write(fdp1, lut[i], base + (i*4));
862 fdp1_write(fdp1, pad, base + (i*4));
865 static void fdp1_set_lut(struct fdp1_dev *fdp1)
867 fdp1_write_lut(fdp1, fdp1_diff_adj, ARRAY_SIZE(fdp1_diff_adj),
869 fdp1_write_lut(fdp1, fdp1_sad_adj, ARRAY_SIZE(fdp1_sad_adj),
871 fdp1_write_lut(fdp1, fdp1_bld_gain, ARRAY_SIZE(fdp1_bld_gain),
873 fdp1_write_lut(fdp1, fdp1_dif_gain, ARRAY_SIZE(fdp1_dif_gain),
875 fdp1_write_lut(fdp1, fdp1_mdet, ARRAY_SIZE(fdp1_mdet),
882 struct fdp1_dev *fdp1 = ctx->fdp1;
918 fdp1_write(fdp1, format, FD1_RPF_FORMAT);
919 fdp1_write(fdp1, q_data->fmt->swap, FD1_RPF_SWAP);
920 fdp1_write(fdp1, picture_size, FD1_RPF_SIZE);
921 fdp1_write(fdp1, pstride, FD1_RPF_PSTRIDE);
922 fdp1_write(fdp1, smsk_addr, FD1_RPF_SMSK_ADDR);
926 fdp1_write(fdp1, job->previous->addrs[0], FD1_RPF0_ADDR_Y);
929 fdp1_write(fdp1, job->active->addrs[0], FD1_RPF1_ADDR_Y);
930 fdp1_write(fdp1, job->active->addrs[1], FD1_RPF1_ADDR_C0);
931 fdp1_write(fdp1, job->active->addrs[2], FD1_RPF1_ADDR_C1);
935 fdp1_write(fdp1, job->next->addrs[0], FD1_RPF2_ADDR_Y);
941 struct fdp1_dev *fdp1 = ctx->fdp1;
989 fdp1_write(fdp1, format, FD1_WPF_FORMAT);
990 fdp1_write(fdp1, rndctl, FD1_WPF_RNDCTL);
991 fdp1_write(fdp1, swap, FD1_WPF_SWAP);
992 fdp1_write(fdp1, pstride, FD1_WPF_PSTRIDE);
994 fdp1_write(fdp1, job->dst->addrs[0], FD1_WPF_ADDR_Y);
995 fdp1_write(fdp1, job->dst->addrs[1], FD1_WPF_ADDR_C0);
996 fdp1_write(fdp1, job->dst->addrs[2], FD1_WPF_ADDR_C1);
1002 struct fdp1_dev *fdp1 = ctx->fdp1;
1011 dprintk(fdp1, "Progressive Mode\n");
1016 dprintk(fdp1, "Adapt2D3D Mode\n");
1032 dprintk(fdp1, "Fixed 3D Mode\n");
1039 dprintk(fdp1, "Fixed 2D Mode\n");
1044 dprintk(fdp1, "Previous Field Mode\n");
1049 dprintk(fdp1, "Next Field Mode\n");
1055 fdp1_write(fdp1, channels, FD1_CTL_CHACT);
1056 fdp1_write(fdp1, opmode, FD1_CTL_OPMODE);
1057 fdp1_write(fdp1, ipcmode, FD1_IPC_MODE);
1069 struct fdp1_dev *fdp1 = ctx->fdp1;
1073 spin_lock_irqsave(&fdp1->device_process_lock, flags);
1076 job = get_queued_job(fdp1);
1082 spin_unlock_irqrestore(&fdp1->device_process_lock, flags);
1087 fdp1_write(fdp1, FD1_CTL_CLKCTRL_CSTP_N, FD1_CTL_CLKCTRL);
1105 fdp1_write(fdp1, FD1_IPC_LMEM_LINEAR, FD1_IPC_LMEM);
1108 fdp1_write(fdp1, FD1_CTL_IRQ_MASK, FD1_CTL_IRQENB);
1113 queue_hw_job(fdp1, job);
1116 fdp1_write(fdp1, FD1_CTL_CMD_STRCMD, FD1_CTL_CMD);
1119 fdp1_write(fdp1, FD1_CTL_REGEND_REGEND, FD1_CTL_REGEND);
1122 fdp1_write(fdp1, FD1_CTL_SGCMD_SGEN, FD1_CTL_SGCMD);
1124 spin_unlock_irqrestore(&fdp1->device_process_lock, flags);
1143 dprintk(ctx->fdp1, "+ Src: %d : Dst: %d\n",
1153 dprintk(ctx->fdp1, "Not enough buffers available\n");
1164 dprintk(ctx->fdp1, "+\n");
1170 fdp1_write(ctx->fdp1, 0, FD1_CTL_SGCMD);
1171 fdp1_write(ctx->fdp1, FD1_CTL_SRESET_SRST, FD1_CTL_SRESET);
1184 struct fdp1_dev *fdp1 = ctx->fdp1;
1188 dprintk(fdp1, "+\n");
1196 job = fdp1_job_alloc(fdp1);
1198 dprintk(fdp1, "No free jobs currently available\n");
1205 dprintk(fdp1, "No input buffers currently available\n");
1207 fdp1_job_free(fdp1, job);
1211 dprintk(fdp1, "+ Buffer en-route...\n");
1249 queue_job(fdp1, job);
1251 dprintk(fdp1, "Job Queued translen = %d\n", ctx->translen);
1265 struct fdp1_dev *fdp1 = ctx->fdp1;
1270 dprintk(fdp1, "+\n");
1282 dprintk(fdp1, "Queued Buffer [%d] last_field:%d\n",
1291 dprintk(fdp1, "No jobs were processed. M2M action complete\n");
1292 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx);
1305 static void device_frame_end(struct fdp1_dev *fdp1,
1310 struct fdp1_job *job = get_hw_queued_job(fdp1);
1312 dprintk(fdp1, "+\n");
1314 ctx = v4l2_m2m_get_curr_priv(fdp1->m2m_dev);
1317 v4l2_err(&fdp1->v4l2_dev,
1333 spin_lock_irqsave(&fdp1->irqlock, flags);
1336 spin_unlock_irqrestore(&fdp1->irqlock, flags);
1339 fdp1_job_free(fdp1, job);
1341 dprintk(fdp1, "curr_ctx->num_processed %d curr_ctx->translen %d\n",
1346 dprintk(ctx->fdp1, "Finishing transaction\n");
1348 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx);
1594 dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n",
1663 v4l2_err(&ctx->fdp1->v4l2_dev, "%s queue busy\n", __func__);
1669 dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n",
1882 dprintk(ctx->fdp1,
1896 dprintk(ctx->fdp1,
1945 ctx->smsk_cpu = dma_alloc_coherent(ctx->fdp1->dev,
1949 dprintk(ctx->fdp1, "Failed to alloc smsk\n");
1974 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
1976 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
1993 dma_free_coherent(ctx->fdp1->dev, ctx->smsk_size,
2005 job = get_queued_job(ctx->fdp1);
2015 job = get_queued_job(ctx->fdp1);
2021 WARN(!list_empty(&ctx->fdp1->queued_job_list),
2024 WARN(!list_empty(&ctx->fdp1->hw_job_list),
2052 src_vq->lock = &ctx->fdp1->dev_mutex;
2053 src_vq->dev = ctx->fdp1->dev;
2066 dst_vq->lock = &ctx->fdp1->dev_mutex;
2067 dst_vq->dev = ctx->fdp1->dev;
2077 struct fdp1_dev *fdp1 = video_drvdata(file);
2083 if (mutex_lock_interruptible(&fdp1->dev_mutex))
2094 ctx->fdp1 = fdp1;
2130 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(fdp1->m2m_dev, ctx, &queue_init);
2138 ret = pm_runtime_resume_and_get(fdp1->dev);
2144 dprintk(fdp1, "Created instance: %p, m2m_ctx: %p\n",
2147 mutex_unlock(&fdp1->dev_mutex);
2156 mutex_unlock(&fdp1->dev_mutex);
2162 struct fdp1_dev *fdp1 = video_drvdata(file);
2165 dprintk(fdp1, "Releasing instance %p\n", ctx);
2170 mutex_lock(&fdp1->dev_mutex);
2172 mutex_unlock(&fdp1->dev_mutex);
2175 pm_runtime_put(fdp1->dev);
2207 struct fdp1_dev *fdp1 = dev_id;
2213 int_status = fdp1_read(fdp1, FD1_CTL_IRQSTA);
2214 cycles = fdp1_read(fdp1, FD1_CTL_VCYCLE_STAT);
2215 ctl_status = fdp1_read(fdp1, FD1_CTL_STATUS);
2220 fdp1_write(fdp1, ~(int_status) & FD1_CTL_IRQ_MASK, FD1_CTL_IRQSTA);
2223 dprintk(fdp1, "IRQ: 0x%x %s%s%s\n", int_status,
2228 dprintk(fdp1, "CycleStatus = %d (%dms)\n",
2229 cycles, cycles/(fdp1->clk_rate/1000));
2231 dprintk(fdp1,
2238 dprintk(fdp1, "***********************************\n");
2247 device_frame_end(fdp1, VB2_BUF_STATE_ERROR);
2249 device_frame_end(fdp1, VB2_BUF_STATE_DONE);
2256 struct fdp1_dev *fdp1;
2265 fdp1 = devm_kzalloc(&pdev->dev, sizeof(*fdp1), GFP_KERNEL);
2266 if (!fdp1)
2269 INIT_LIST_HEAD(&fdp1->free_job_list);
2270 INIT_LIST_HEAD(&fdp1->queued_job_list);
2271 INIT_LIST_HEAD(&fdp1->hw_job_list);
2274 for (i = 0; i < ARRAY_SIZE(fdp1->jobs); i++)
2275 list_add(&fdp1->jobs[i].list, &fdp1->free_job_list);
2277 mutex_init(&fdp1->dev_mutex);
2279 spin_lock_init(&fdp1->irqlock);
2280 spin_lock_init(&fdp1->device_process_lock);
2281 fdp1->dev = &pdev->dev;
2282 platform_set_drvdata(pdev, fdp1);
2285 fdp1->regs = devm_platform_ioremap_resource(pdev, 0);
2286 if (IS_ERR(fdp1->regs))
2287 return PTR_ERR(fdp1->regs);
2293 fdp1->irq = ret;
2295 ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0,
2296 dev_name(&pdev->dev), fdp1);
2298 dev_err(&pdev->dev, "cannot claim IRQ %d\n", fdp1->irq);
2305 fdp1->fcp = rcar_fcp_get(fcp_node);
2307 if (IS_ERR(fdp1->fcp)) {
2309 PTR_ERR(fdp1->fcp));
2310 return PTR_ERR(fdp1->fcp);
2321 fdp1->clk_rate = clk_get_rate(clk);
2325 ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev);
2327 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n");
2332 fdp1->m2m_dev = v4l2_m2m_init(&m2m_ops);
2333 if (IS_ERR(fdp1->m2m_dev)) {
2334 v4l2_err(&fdp1->v4l2_dev, "Failed to init mem2mem device\n");
2335 ret = PTR_ERR(fdp1->m2m_dev);
2340 fdp1->vfd = fdp1_videodev;
2341 vfd = &fdp1->vfd;
2342 vfd->lock = &fdp1->dev_mutex;
2343 vfd->v4l2_dev = &fdp1->v4l2_dev;
2344 video_set_drvdata(vfd, fdp1);
2349 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n");
2353 v4l2_info(&fdp1->v4l2_dev, "Device registered as /dev/video%d\n",
2358 ret = pm_runtime_resume_and_get(fdp1->dev);
2362 hw_version = fdp1_read(fdp1, FD1_IP_INTDATA);
2365 dprintk(fdp1, "FDP1 Version R-Car Gen2\n");
2368 dprintk(fdp1, "FDP1 Version R-Car M3-W\n");
2371 dprintk(fdp1, "FDP1 Version R-Car H3\n");
2374 dprintk(fdp1, "FDP1 Version R-Car M3-N\n");
2377 dprintk(fdp1, "FDP1 Version R-Car E3\n");
2380 dev_err(fdp1->dev, "FDP1 Unidentifiable (0x%08x)\n",
2385 pm_runtime_put(fdp1->dev);
2390 pm_runtime_disable(fdp1->dev);
2393 v4l2_m2m_release(fdp1->m2m_dev);
2396 v4l2_device_unregister(&fdp1->v4l2_dev);
2399 rcar_fcp_put(fdp1->fcp);
2405 struct fdp1_dev *fdp1 = platform_get_drvdata(pdev);
2407 v4l2_m2m_release(fdp1->m2m_dev);
2408 video_unregister_device(&fdp1->vfd);
2409 v4l2_device_unregister(&fdp1->v4l2_dev);
2411 rcar_fcp_put(fdp1->fcp);
2416 struct fdp1_dev *fdp1 = dev_get_drvdata(dev);
2418 rcar_fcp_disable(fdp1->fcp);
2425 struct fdp1_dev *fdp1 = dev_get_drvdata(dev);
2428 fdp1_set_lut(fdp1);
2430 return rcar_fcp_enable(fdp1->fcp);
2440 { .compatible = "renesas,fdp1" },