platform/renesas/rcar_drif.c

128 	(&((sdr)->ch[!(ch_num)]->buf[(idx)]))
130 #define for_each_rcar_drif_channel(ch, ch_mask)			\
131 	for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
231 	struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
241 static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
243 	writel(data, ch->base + offset);
246 static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
248 	return readl(ch->base + offset);
257 		if (sdr->ch[i]->dmach) {
258 			dma_release_channel(sdr->ch[i]->dmach);
259 			sdr->ch[i]->dmach = NULL;
271 		struct rcar_drif *ch = sdr->ch[i];
273 		ch->dmach = dma_request_chan(&ch->pdev->dev, "rx");
274 		if (IS_ERR(ch->dmach)) {
275 			ret = PTR_ERR(ch->dmach);
278 					  "ch%u: dma channel req failed: %pe\n",
279 					  i, ch->dmach);
280 			ch->dmach = NULL;
286 		dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
288 		ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
290 			rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
324 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
328 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
330 		rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
331 			  i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
358 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
362 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
364 		rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
365 			  i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
366 			  rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
377 		struct rcar_drif *ch = sdr->ch[i];
380 		if (ch->buf[0].addr) {
381 			dma_free_coherent(&ch->pdev->dev,
383 				ch->buf[0].addr, ch->dma_handle);
384 			ch->buf[0].addr = NULL;
397 		struct rcar_drif *ch = sdr->ch[i];
400 		addr = dma_alloc_coherent(&ch->pdev->dev,
402 				&ch->dma_handle, GFP_KERNEL);
405 			"ch%u: dma alloc failed. num hwbufs %u size %u\n",
412 			ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
413 			ch->buf[j].status = 0;
501 static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
505 	ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
508 	str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
511 		rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
514 		ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
521 	struct rcar_drif *ch = dma_async_param;
522 	struct rcar_drif_sdr *sdr = ch->sdr;
538 	rcar_drif_channel_complete(ch, idx);
541 		buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
542 				&ch->buf[idx];
543 		buf[1] = ch->num ? &ch->buf[idx] :
544 				to_rcar_drif_buf_pair(sdr, ch->num, idx);
561 		buf[0] = &ch->buf[idx];
573 	rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
594 static int rcar_drif_qbuf(struct rcar_drif *ch)
596 	struct rcar_drif_sdr *sdr = ch->sdr;
597 	dma_addr_t addr = ch->dma_handle;
603 	rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
608 		rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
614 	rxd->callback_param = ch;
617 		rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
621 	dma_async_issue_pending(ch->dmach);
639 		ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
642 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
647 		ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
650 			rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
651 				  rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
667 		ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
669 		rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
674 		ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
678 			"ch%u: failed to disable rx. ctr 0x%08x\n",
679 			i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
684 static void rcar_drif_stop_channel(struct rcar_drif *ch)
687 	rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
690 	dmaengine_terminate_sync(ch->dmach);
702 		rcar_drif_stop_channel(sdr->ch[i]);
706 static int rcar_drif_start_channel(struct rcar_drif *ch)
708 	struct rcar_drif_sdr *sdr = ch->sdr;
713 	rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
714 	ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
717 		rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
718 			  ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
723 	ret = rcar_drif_qbuf(ch);
730 	rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
733 	rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
746 		ret = rcar_drif_start_channel(sdr->ch[i]);
763 		rcar_drif_stop_channel(sdr->ch[i]);
779 		ret = clk_prepare_enable(sdr->ch[i]->clk);
825 		clk_disable_unprepare(sdr->ch[i]->clk);
853 		clk_disable_unprepare(sdr->ch[i]->clk);
1260 	struct rcar_drif *ch;
1270 	ch = platform_get_drvdata(pdev);
1271 	if (ch) {
1273 		ch->sdr = sdr;
1276 		sdr->ch[ch->num] = ch;
1277 		sdr->hw_ch_mask |= BIT(ch->num);
1374 	struct rcar_drif *ch;
1379 	ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1380 	if (!ch)
1383 	ch->pdev = pdev;
1386 	ch->clk = devm_clk_get(&pdev->dev, "fck");
1387 	if (IS_ERR(ch->clk)) {
1388 		ret = PTR_ERR(ch->clk);
1394 	ch->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1395 	if (IS_ERR(ch->base))
1396 		return PTR_ERR(ch->base);
1398 	ch->start = res->start;
1399 	platform_set_drvdata(pdev, ch);
1406 			ch->num = 1;	/* Primary bond is channel 0 always */
1418 	ch->sdr = sdr;
1422 	sdr->ch[ch->num] = ch;
1423 	sdr->hw_ch_mask = BIT(ch->num);
1439 	struct rcar_drif *ch = platform_get_drvdata(pdev);
1440 	struct rcar_drif_sdr *sdr = ch->sdr;
1443 	if (ch->num)