Lines Matching refs:ALIGN
56 (MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN((width), 16) * 3)
76 (ALIGN((height), 16) * 32)
102 (MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * (ALIGN(width, 64) + 8) * 2)
106 (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS))
110 (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS))
128 (ALIGN(width, LCU_MIN_SIZE_PELS) / LCU_MIN_SIZE_PELS))
164 (((ALIGN(width, 64) + 8) * 10 * 2)) /* small line */
180 ALIGN((ALIGN(height, 16) / (4 / 2)) * 64, 32)
182 ((ALIGN(width, 16) + 8) * 10 * 2)
184 ((ALIGN(ALIGN(width, 16), 64) + 8) * 10 * 2)
186 ((ALIGN(width, 16) >> 4) * 64)
188 ((ALIGN(ALIGN(width, 16), 64) >> 6) * 176)
190 (((ALIGN(width, 16) >> 4) * 64 / 2) + 256)
192 (((ALIGN(ALIGN(width, 16), 64) >> 6) * 64 * 8) + 256)
212 #define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, 32)
248 ALIGN(width, macrotiling_size) / macrotiling_size * 256;
250 ALIGN(opb_wr_top_line_luma_buf_size, HFI_DMA_ALIGNMENT) +
253 max(opb_wr_top_line_luma_buf_size, (32 * ALIGN(height, 16)));
255 opb_lb_wr_llb_y_buffer_size = ALIGN((ALIGN(height, 16) / 2) * 64, 32);
280 size_bin_hdr = ALIGN(size_bin_hdr, HFI_DMA_ALIGNMENT);
281 size_bin_res = ALIGN(size_bin_res, HFI_DMA_ALIGNMENT);
289 u32 aligned_width = ALIGN(width, 16);
290 u32 aligned_height = ALIGN(height, 16);
310 size_bin_hdr = ALIGN(size_bin_hdr, HFI_DMA_ALIGNMENT);
311 size_bin_res = ALIGN(size_bin_res, HFI_DMA_ALIGNMENT);
319 u32 aligned_width = ALIGN(width, 16);
320 u32 aligned_height = ALIGN(height, 16);
331 u32 aligned_width = ALIGN(width, 16);
332 u32 aligned_height = ALIGN(height, 16);
349 size = ALIGN(binbuffer1_size + binbufer2_size,
374 aligned_width = ALIGN(width, 32);
375 aligned_height = ALIGN(height, 32);
376 mbs_per_frame = (ALIGN(aligned_height, 16) *
377 ALIGN(aligned_width, 16)) / 256;
400 return ALIGN(frame_size, SZ_4K);
411 aligned_width = ALIGN(width, lcu_size);
412 aligned_height = ALIGN(height, lcu_size);
416 bitstream_size = ALIGN(bitstream_size, HFI_DMA_ALIGNMENT);
421 bitbin_size = ALIGN(bitbin_size, HFI_DMA_ALIGNMENT);
425 bitbin_size = ALIGN(bitstream_size, HFI_DMA_ALIGNMENT);
433 size_single_pipe = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT);
436 padded_bin_size = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT);
438 size_single_pipe = ALIGN(size_single_pipe, HFI_DMA_ALIGNMENT);
440 size = ALIGN(bitbin_size, HFI_DMA_ALIGNMENT) *
476 col_mv_aligned_width = ALIGN(col_mv_aligned_width, 16);
477 col_zero_aligned_width = ALIGN(col_zero_aligned_width, 16);
480 col_zero_size = ALIGN(col_zero_size, 64);
482 col_zero_size = ALIGN(col_zero_size, 512);
484 size_colloc = ALIGN(size_colloc, 64);
486 size_colloc = ALIGN(size_colloc, 512);
496 u32 aligned_height = ALIGN(height, 32);
504 u32 aligned_height = ALIGN(height, 32);
523 ALIGN(size_bse, HFI_DMA_ALIGNMENT) +
524 ALIGN(size_vpp, HFI_DMA_ALIGNMENT) +
525 ALIGN(SIZE_HW_PIC(SIZE_H264D_HW_PIC_T), HFI_DMA_ALIGNMENT) +
526 ALIGN(SIZE_H264D_LB_FE_TOP_DATA(width, height),
528 ALIGN(SIZE_H264D_LB_FE_TOP_CTRL(width, height),
530 ALIGN(SIZE_H264D_LB_FE_LEFT_CTRL(width, height),
532 ALIGN(SIZE_H264D_LB_SE_TOP_CTRL(width, height),
534 ALIGN(SIZE_H264D_LB_SE_LEFT_CTRL(width, height),
536 ALIGN(SIZE_H264D_LB_PE_TOP_DATA(width, height),
538 ALIGN(SIZE_H264D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) +
539 ALIGN(SIZE_H264D_LB_RECON_DMA_METADATA_WR(width, height),
541 ALIGN(SIZE_H264D_QP(width, height), HFI_DMA_ALIGNMENT);
543 return ALIGN(size, HFI_DMA_ALIGNMENT);
550 size = (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
551 (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
556 return ALIGN(size, HFI_DMA_ALIGNMENT);
563 size = (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
564 (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
567 size = ALIGN(size, 4);
569 size = ALIGN(size, HFI_DMA_ALIGNMENT);
581 size = ALIGN(((((width + 15) >> 4) * ((height + 15) >> 4)) << 8), 512);
596 ALIGN(size_bse, HFI_DMA_ALIGNMENT) +
597 ALIGN(size_vpp, HFI_DMA_ALIGNMENT) +
598 ALIGN(NUM_HW_PIC_BUF * 20 * 22 * 4, HFI_DMA_ALIGNMENT) +
599 ALIGN(2 * sizeof(u16) *
600 (ALIGN(width, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS) *
601 (ALIGN(height, LCU_MAX_SIZE_PELS) / LCU_MIN_SIZE_PELS),
603 ALIGN(SIZE_HW_PIC(SIZE_H265D_HW_PIC_T), HFI_DMA_ALIGNMENT) +
604 ALIGN(SIZE_H265D_LB_FE_TOP_DATA(width, height),
606 ALIGN(SIZE_H265D_LB_FE_TOP_CTRL(width, height),
608 ALIGN(SIZE_H265D_LB_FE_LEFT_CTRL(width, height),
610 ALIGN(size_h265d_lb_se_left_ctrl(width, height),
612 ALIGN(SIZE_H265D_LB_SE_TOP_CTRL(width, height),
614 ALIGN(SIZE_H265D_LB_PE_TOP_DATA(width, height),
616 ALIGN(SIZE_H265D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) +
617 ALIGN(SIZE_H265D_LB_VSP_LEFT(width, height),
619 ALIGN(SIZE_H265D_LB_RECON_DMA_METADATA_WR(width, height),
622 ALIGN(SIZE_H265D_QP(width, height), HFI_DMA_ALIGNMENT);
624 return ALIGN(size, HFI_DMA_ALIGNMENT);
668 size += ALIGN(size_vpxd_lb_fe_left_ctrl(width, height),
670 ALIGN(size_vpxd_lb_se_left_ctrl(width, height),
672 ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) +
673 ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
675 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height),
677 ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height),
679 ALIGN(SIZE_VP8D_LB_PE_TOP_DATA(width, height),
681 ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),
698 ALIGN(size_vpxd_lb_fe_left_ctrl(width, height),
700 ALIGN(size_vpxd_lb_se_left_ctrl(width, height),
702 ALIGN(SIZE_VP9D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) +
703 ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
705 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height),
707 ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height),
709 ALIGN(SIZE_VP9D_LB_PE_TOP_DATA(width, height),
711 ALIGN(SIZE_VP9D_LB_FE_TOP_DATA(width, height),
729 ALIGN(size_vpxd_lb_fe_left_ctrl(width, height),
731 ALIGN(size_vpxd_lb_se_left_ctrl(width, height),
733 ALIGN(SIZE_VP8D_LB_VSP_TOP(width, height), HFI_DMA_ALIGNMENT) +
734 ALIGN(SIZE_VPXD_LB_FE_TOP_CTRL(width, height),
736 2 * ALIGN(SIZE_VPXD_LB_RECON_DMA_METADATA_WR(width, height),
738 ALIGN(SIZE_VPXD_LB_SE_TOP_CTRL(width, height),
740 ALIGN(SIZE_VP8D_LB_PE_TOP_DATA(width, height),
742 ALIGN(SIZE_VP8D_LB_FE_TOP_DATA(width, height),
780 slice_info_bufsize = ALIGN(slice_info_bufsize, HFI_DMA_ALIGNMENT);
781 line_buf_ctrl_size = ALIGN(width_coded, HFI_DMA_ALIGNMENT);
782 line_buf_ctrl_size_buffid2 = ALIGN(width_coded, HFI_DMA_ALIGNMENT);
798 ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes;
802 ALIGN(leftline_buf_ctrl_size, HFI_DMA_ALIGNMENT);
811 ALIGN(topline_buf_ctrl_size_FE, HFI_DMA_ALIGNMENT);
820 ALIGN(leftline_buf_meta_recony, HFI_DMA_ALIGNMENT);
824 linebuf_meta_recon_uv = ALIGN(linebuf_meta_recon_uv, HFI_DMA_ALIGNMENT);
828 ALIGN(line_buf_recon_pix_size, HFI_DMA_ALIGNMENT);
829 slice_cmd_buffer_size = ALIGN(20480, HFI_DMA_ALIGNMENT);
834 ALIGN(col_mv_buf_size, HFI_DMA_ALIGNMENT) * (num_ref + 1);
839 ALIGN(h265e_colrcbuf_size, HFI_DMA_ALIGNMENT) *
842 h265e_colrcbuf_size = ALIGN(h265e_colrcbuf_size, HFI_DMA_ALIGNMENT) *
850 ALIGN(h265e_framerc_bufsize, HFI_DMA_ALIGNMENT) *
853 h265e_framerc_bufsize = ALIGN(h265e_framerc_bufsize, 512) *
857 ALIGN(h265e_lcubitcnt_bufsize, HFI_DMA_ALIGNMENT);
860 ALIGN(h265e_lcubitmap_bufsize, HFI_DMA_ALIGNMENT);
862 line_buf_sde_size = ALIGN(line_buf_sde_size, HFI_DMA_ALIGNMENT);
870 se_stats_bufsize = ALIGN(se_stats_bufsize, HFI_DMA_ALIGNMENT) * 2;
878 ALIGN(override_buffer_size, HFI_DMA_ALIGNMENT) * 2;
886 ALIGN(topline_bufsize_fe_1stg_sao, HFI_DMA_ALIGNMENT);
931 return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels),
938 return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels),
945 return ALIGN(metadata_stride * metadata_buf_height, SZ_4K);
958 aligned_height = ALIGN(height, HFI_VENUS_HEIGHT_ALIGNMENT);
960 chroma_height = ALIGN(chroma_height,
962 aligned_width = ALIGN(width, HFI_VENUS_WIDTH_ALIGNMENT);
1017 return ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264
1023 return ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + H265_NUM_TILE
1029 return ALIGN(VP8_NUM_PROBABILITY_TABLE_BUF * VP8_PROB_TABLE_SIZE,
1036 ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE,
1038 ALIGN(HFI_IRIS2_VP9D_COMV_SIZE, HFI_DMA_ALIGNMENT) +
1039 ALIGN(MAX_SUPERFRAME_HEADER_LEN, HFI_DMA_ALIGNMENT) +
1040 ALIGN(VP9_UDC_HEADER_BUF_SIZE, HFI_DMA_ALIGNMENT) +
1041 ALIGN(VP9_NUM_FRAME_INFO_BUF * CCE_TILE_OFFSET_SIZE,
1132 num_mbs = (ALIGN(height, 16) * ALIGN(width, 16)) / 256;
1153 return ALIGN(frame_size, SZ_4K);