Lines Matching refs:output

39 	struct vfe_output *output = &line->output;
47 output->gen1.wait_sof = 1;
50 time = wait_for_completion_timeout(&output->sof, msecs_to_jiffies(VFE_NEXT_SOF_MS));
55 for (i = 0; i < output->wm_num; i++)
56 vfe->ops_gen1->wm_enable(vfe, output->wm_idx[i], 0);
59 output->wait_reg_update = 1;
62 time = wait_for_completion_timeout(&output->reg_update, msecs_to_jiffies(VFE_NEXT_SOF_MS));
69 vfe->ops_gen1->wm_frame_based(vfe, output->wm_idx[0], 0);
70 vfe->ops_gen1->bus_disconnect_wm_from_rdi(vfe, output->wm_idx[0], line->id);
71 vfe->ops_gen1->enable_irq_wm_line(vfe, output->wm_idx[0], line->id, 0);
72 vfe->ops_gen1->set_cgc_override(vfe, output->wm_idx[0], 0);
75 for (i = 0; i < output->wm_num; i++) {
76 vfe->ops_gen1->wm_line_based(vfe, output->wm_idx[i], NULL, i, 0);
77 vfe->ops_gen1->set_cgc_override(vfe, output->wm_idx[i], 0);
83 vfe->ops_gen1->set_xbar_cfg(vfe, output, 0);
121 struct vfe_output *output, u8 sync,
128 output->gen1.active_buf = 0;
130 for (i = 0; i < output->wm_num; i++) {
131 if (output->buf[0])
132 ping_addr = output->buf[0]->addr[i];
136 if (output->buf[1])
137 pong_addr = output->buf[1]->addr[i];
141 vfe->ops_gen1->wm_set_ping_addr(vfe, output->wm_idx[i], ping_addr);
142 vfe->ops_gen1->wm_set_pong_addr(vfe, output->wm_idx[i], pong_addr);
144 vfe->ops_gen1->bus_reload_wm(vfe, output->wm_idx[i]);
149 struct vfe_output *output,
156 output->drop_update_idx++;
157 output->drop_update_idx %= VFE_FRAME_DROP_UPDATES;
158 drop_period = VFE_FRAME_DROP_VAL + output->drop_update_idx;
160 for (i = 0; i < output->wm_num; i++) {
161 vfe->ops_gen1->wm_set_framedrop_period(vfe, output->wm_idx[i], drop_period);
162 vfe->ops_gen1->wm_set_framedrop_pattern(vfe, output->wm_idx[i], drop_pattern);
165 vfe->ops->reg_update(vfe, container_of(output, struct vfe_line, output)->id);
171 struct vfe_output *output = &line->output;
197 if (output->state > VFE_OUTPUT_RESERVED) {
198 dev_err(vfe->camss->dev, "Output is not in reserved state %d\n", output->state);
202 output->state = VFE_OUTPUT_IDLE;
204 output->buf[0] = vfe_buf_get_pending(output);
205 output->buf[1] = vfe_buf_get_pending(output);
207 if (!output->buf[0] && output->buf[1]) {
208 output->buf[0] = output->buf[1];
209 output->buf[1] = NULL;
212 if (output->buf[0])
213 output->state = VFE_OUTPUT_SINGLE;
215 if (output->buf[1])
216 output->state = VFE_OUTPUT_CONTINUOUS;
218 switch (output->state) {
220 vfe_output_frame_drop(vfe, output, 1 << frame_skip);
223 vfe_output_frame_drop(vfe, output, 3 << frame_skip);
226 vfe_output_frame_drop(vfe, output, 0);
230 output->sequence = 0;
231 output->gen1.wait_sof = 0;
232 output->wait_reg_update = 0;
233 reinit_completion(&output->sof);
234 reinit_completion(&output->reg_update);
236 vfe_output_init_addrs(vfe, output, 0, line);
239 vfe->ops_gen1->set_cgc_override(vfe, output->wm_idx[0], 1);
240 vfe->ops_gen1->enable_irq_wm_line(vfe, output->wm_idx[0], line->id, 1);
241 vfe->ops_gen1->bus_connect_wm_to_rdi(vfe, output->wm_idx[0], line->id);
242 vfe->ops_gen1->wm_set_subsample(vfe, output->wm_idx[0]);
244 vfe->ops_gen1->wm_set_ub_cfg(vfe, output->wm_idx[0],
245 (ub_size + 1) * output->wm_idx[0], ub_size);
246 vfe->ops_gen1->wm_frame_based(vfe, output->wm_idx[0], 1);
247 vfe->ops_gen1->wm_enable(vfe, output->wm_idx[0], 1);
248 vfe->ops_gen1->bus_reload_wm(vfe, output->wm_idx[0]);
250 ub_size /= output->wm_num;
251 for (i = 0; i < output->wm_num; i++) {
252 vfe->ops_gen1->set_cgc_override(vfe, output->wm_idx[i], 1);
253 vfe->ops_gen1->wm_set_subsample(vfe, output->wm_idx[i]);
254 vfe->ops_gen1->wm_set_ub_cfg(vfe, output->wm_idx[i],
255 (ub_size + 1) * output->wm_idx[i], ub_size);
256 vfe->ops_gen1->wm_line_based(vfe, output->wm_idx[i],
258 vfe->ops_gen1->wm_enable(vfe, output->wm_idx[i], 1);
259 vfe->ops_gen1->bus_reload_wm(vfe, output->wm_idx[i]);
265 vfe->ops_gen1->set_xbar_cfg(vfe, output, 1);
283 struct vfe_output *output;
291 output = &line->output;
292 if (output->state > VFE_OUTPUT_RESERVED) {
296 output->state = VFE_OUTPUT_RESERVED;
298 output->gen1.active_buf = 0;
305 output->wm_num = 2;
308 output->wm_num = 1;
312 for (i = 0; i < output->wm_num; i++) {
318 output->wm_idx[i] = wm_idx;
321 output->drop_update_idx = 0;
329 vfe_release_wm(vfe, output->wm_idx[i]);
330 output->state = VFE_OUTPUT_OFF;
384 struct vfe_output *output, u8 sync,
390 for (i = 0; i < output->wm_num; i++) {
391 if (output->buf[0])
392 addr = output->buf[0]->addr[i];
396 vfe->ops_gen1->wm_set_ping_addr(vfe, output->wm_idx[i], addr);
398 vfe->ops_gen1->bus_reload_wm(vfe, output->wm_idx[i]);
403 struct vfe_output *output, u8 sync,
409 for (i = 0; i < output->wm_num; i++) {
410 if (output->buf[1])
411 addr = output->buf[1]->addr[i];
415 vfe->ops_gen1->wm_set_pong_addr(vfe, output->wm_idx[i], addr);
417 vfe->ops_gen1->bus_reload_wm(vfe, output->wm_idx[i]);
422 struct vfe_output *output)
424 switch (output->state) {
426 vfe_output_frame_drop(vfe, output, 3);
432 output->state);
438 struct vfe_output *output)
440 switch (output->state) {
442 output->state = VFE_OUTPUT_SINGLE;
443 vfe_output_frame_drop(vfe, output, 1);
446 output->state = VFE_OUTPUT_STOPPING;
447 vfe_output_frame_drop(vfe, output, 0);
452 output->state);
458 struct vfe_output *output,
464 switch (output->state) {
466 inactive_idx = !output->gen1.active_buf;
468 if (!output->buf[inactive_idx]) {
469 output->buf[inactive_idx] = new_buf;
472 vfe_output_update_pong_addr(vfe, output, 0, line);
474 vfe_output_update_ping_addr(vfe, output, 0, line);
476 vfe_output_frame_drop(vfe, output, 3);
477 output->state = VFE_OUTPUT_CONTINUOUS;
479 vfe_buf_add_pending(output, new_buf);
486 if (!output->buf[0]) {
487 output->buf[0] = new_buf;
489 vfe_output_init_addrs(vfe, output, 1, line);
490 vfe_output_frame_drop(vfe, output, 1);
492 output->state = VFE_OUTPUT_SINGLE;
494 vfe_buf_add_pending(output, new_buf);
502 vfe_buf_add_pending(output, new_buf);
524 struct vfe_output *output;
528 output = &vfe->line[line_id].output;
529 if (output->gen1.wait_sof) {
530 output->gen1.wait_sof = 0;
531 complete(&output->sof);
543 struct vfe_output *output;
550 output = &line->output;
552 if (output->wait_reg_update) {
553 output->wait_reg_update = 0;
554 complete(&output->reg_update);
559 if (output->state == VFE_OUTPUT_STOPPING) {
561 if (output->last_buffer) {
562 vb2_buffer_done(&output->last_buffer->vb.vb2_buf,
564 output->last_buffer = NULL;
566 output->state = VFE_OUTPUT_IDLE;
571 output->buf[0] = vfe_buf_get_pending(output);
572 output->buf[1] = vfe_buf_get_pending(output);
574 if (!output->buf[0] && output->buf[1]) {
575 output->buf[0] = output->buf[1];
576 output->buf[1] = NULL;
579 if (output->buf[0])
580 output->state = VFE_OUTPUT_SINGLE;
582 if (output->buf[1])
583 output->state = VFE_OUTPUT_CONTINUOUS;
585 switch (output->state) {
587 vfe_output_frame_drop(vfe, output, 2);
590 vfe_output_frame_drop(vfe, output, 3);
593 vfe_output_frame_drop(vfe, output, 0);
597 vfe_output_init_addrs(vfe, output, 1, &vfe->line[line_id]);
611 struct vfe_output *output;
627 output = &vfe->line[vfe->wm_output_map[wm]].output;
629 if (output->gen1.active_buf == active_index && 0) {
634 output->gen1.active_buf = active_index;
636 ready_buf = output->buf[!active_index];
640 !active_index, output->state);
645 ready_buf->vb.sequence = output->sequence++;
648 output->buf[!active_index] = vfe_buf_get_pending(output);
649 if (!output->buf[!active_index]) {
652 vfe_buf_update_wm_on_last(vfe, output);
654 new_addr = output->buf[!active_index]->addr;
655 vfe_buf_update_wm_on_next(vfe, output);
659 for (i = 0; i < output->wm_num; i++)
660 vfe->ops_gen1->wm_set_ping_addr(vfe, output->wm_idx[i], new_addr[i]);
662 for (i = 0; i < output->wm_num; i++)
663 vfe->ops_gen1->wm_set_pong_addr(vfe, output->wm_idx[i], new_addr[i]);
667 if (output->state == VFE_OUTPUT_STOPPING)
668 output->last_buffer = ready_buf;
692 struct vfe_output *output;
695 output = &line->output;
699 vfe_buf_update_wm_on_new(vfe, output, buf, line);