Lines Matching defs:isc
52 #include "microchip-isc-regs.h"
53 #include "microchip-isc.h"
230 static void isc_sama7g5_config_csc(struct isc_device *isc)
232 struct regmap *regmap = isc->regmap;
235 regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc,
237 regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc,
239 regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc,
241 regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc,
243 regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc,
245 regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc,
249 static void isc_sama7g5_config_cbc(struct isc_device *isc)
251 struct regmap *regmap = isc->regmap;
254 regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness);
255 regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast);
261 static void isc_sama7g5_config_cc(struct isc_device *isc)
263 struct regmap *regmap = isc->regmap;
274 static void isc_sama7g5_config_ctrls(struct isc_device *isc,
277 struct isc_ctrls *ctrls = &isc->ctrls;
285 static void isc_sama7g5_config_dpc(struct isc_device *isc)
287 u32 bay_cfg = isc->config.sd_format->cfa_baycfg;
288 struct regmap *regmap = isc->regmap;
296 static void isc_sama7g5_config_gam(struct isc_device *isc)
298 struct regmap *regmap = isc->regmap;
304 static void isc_sama7g5_config_rlp(struct isc_device *isc)
306 struct regmap *regmap = isc->regmap;
307 u32 rlp_mode = isc->config.rlp_cfg_mode;
309 regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp,
314 static void isc_sama7g5_adapt_pipeline(struct isc_device *isc)
316 isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE;
336 static int xisc_parse_dt(struct device *dev, struct isc_device *isc)
345 INIT_LIST_HEAD(&isc->subdev_entities);
390 list_add_tail(&subdev_entity->list, &isc->subdev_entities);
400 struct isc_device *isc;
407 isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL);
408 if (!isc)
411 platform_set_drvdata(pdev, isc);
412 isc->dev = dev;
418 isc->regmap = devm_regmap_init_mmio(dev, io_base, µchip_isc_regmap_config);
419 if (IS_ERR(isc->regmap)) {
420 ret = PTR_ERR(isc->regmap);
430 "microchip-sama7g5-xisc", isc);
437 isc->gamma_table = isc_sama7g5_gamma_table;
438 isc->gamma_max = 0;
440 isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH;
441 isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT;
443 isc->config_dpc = isc_sama7g5_config_dpc;
444 isc->config_csc = isc_sama7g5_config_csc;
445 isc->config_cbc = isc_sama7g5_config_cbc;
446 isc->config_cc = isc_sama7g5_config_cc;
447 isc->config_gam = isc_sama7g5_config_gam;
448 isc->config_rlp = isc_sama7g5_config_rlp;
449 isc->config_ctrls = isc_sama7g5_config_ctrls;
451 isc->adapt_pipeline = isc_sama7g5_adapt_pipeline;
453 isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET;
454 isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET;
455 isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET;
456 isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET;
457 isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET;
458 isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET;
459 isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET;
460 isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET;
461 isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET;
463 isc->controller_formats = sama7g5_controller_formats;
464 isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats);
465 isc->formats_list = sama7g5_formats_list;
466 isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list);
468 /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */
469 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32;
471 /* sama7g5-isc : ISPCK does not exist, ISC is clocked by MCK */
472 isc->ispck_required = false;
474 ret = microchip_isc_pipeline_init(isc);
478 isc->hclock = devm_clk_get(dev, "hclock");
479 if (IS_ERR(isc->hclock)) {
480 ret = PTR_ERR(isc->hclock);
485 ret = clk_prepare_enable(isc->hclock);
491 ret = microchip_isc_clk_init(isc);
493 dev_err(dev, "failed to init isc clock: %d\n", ret);
497 ret = v4l2_device_register(dev, &isc->v4l2_dev);
503 ret = xisc_parse_dt(dev, isc);
509 if (list_empty(&isc->subdev_entities)) {
515 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
520 v4l2_async_nf_init(&subdev_entity->notifier, &isc->v4l2_dev);
542 if (video_is_registered(&isc->video_dev))
546 regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver);
548 ret = isc_mc_init(isc, ver);
561 isc_mc_cleanup(isc);
564 microchip_isc_subdev_cleanup(isc);
567 v4l2_device_unregister(&isc->v4l2_dev);
570 clk_disable_unprepare(isc->hclock);
572 microchip_isc_clk_cleanup(isc);
579 struct isc_device *isc = platform_get_drvdata(pdev);
583 isc_mc_cleanup(isc);
585 microchip_isc_subdev_cleanup(isc);
587 v4l2_device_unregister(&isc->v4l2_dev);
589 clk_disable_unprepare(isc->hclock);
591 microchip_isc_clk_cleanup(isc);
596 struct isc_device *isc = dev_get_drvdata(dev);
598 clk_disable_unprepare(isc->hclock);
605 struct isc_device *isc = dev_get_drvdata(dev);
608 ret = clk_prepare_enable(isc->hclock);
621 { .compatible = "microchip,sama7g5-isc" },