mediatek/jpeg/mtk_jpeg_core.c

1457 	struct mtk_jpegenc_comp_dev *comp_jpeg;
1465 		comp_jpeg = jpeg->enc_hw_dev[i];
1466 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
1468 			comp_jpeg->hw_state = MTK_JPEG_HW_BUSY;
1504 	struct mtk_jpegdec_comp_dev *comp_jpeg;
1512 		comp_jpeg = jpeg->dec_hw_dev[i];
1513 		if (comp_jpeg->hw_state == MTK_JPEG_HW_IDLE) {
1515 			comp_jpeg->hw_state = MTK_JPEG_HW_BUSY;
1581 	struct mtk_jpegenc_comp_dev *comp_jpeg[MTK_JPEGENC_HW_MAX];
1594 		comp_jpeg[i] = jpeg->enc_hw_dev[i];
1624 	ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
1631 	ret = clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk);
1641 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
1644 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
1649 	mtk_jpeg_enc_reset(comp_jpeg[hw_id]->reg_base);
1651 			     comp_jpeg[hw_id]->reg_base,
1654 			     comp_jpeg[hw_id]->reg_base,
1656 	mtk_jpeg_set_enc_params(ctx, comp_jpeg[hw_id]->reg_base);
1657 	mtk_jpeg_enc_start(comp_jpeg[hw_id]->reg_base);
1659 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
1678 	struct mtk_jpegdec_comp_dev *comp_jpeg[MTK_JPEGDEC_HW_MAX];
1689 		comp_jpeg[i] = jpeg->dec_hw_dev[i];
1734 	ret = pm_runtime_get_sync(comp_jpeg[hw_id]->dev);
1741 	ret = clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk);
1760 	schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work,
1763 	spin_lock_irqsave(&comp_jpeg[hw_id]->hw_lock, flags);
1765 	mtk_jpeg_dec_reset(comp_jpeg[hw_id]->reg_base);
1766 	mtk_jpeg_dec_set_config(comp_jpeg[hw_id]->reg_base,
1771 	mtk_jpeg_dec_start(comp_jpeg[hw_id]->reg_base);
1773 	spin_unlock_irqrestore(&comp_jpeg[hw_id]->hw_lock, flags);
1778 	clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk);
1780 	pm_runtime_put(comp_jpeg[hw_id]->dev);