chips-media/wave5/wave5-hw.c

1525 	struct enc_wave_param *p_param = &p_open_param->wave_param;
1566 	wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width,
1575 	reg_val = p_param->profile |
1576 		(p_param->level << 3) |
1577 		(p_param->internal_bit_depth << 14);
1579 		reg_val |= (p_param->tier << 12) |
1580 			(p_param->tmvp_enable << 23) |
1581 			(p_param->sao_enable << 24) |
1582 			(p_param->skip_intra_trans << 25) |
1583 			(p_param->strong_intra_smooth_enable << 27) |
1584 			(p_param->en_still_picture << 30);
1587 	reg_val = (p_param->lossless_enable) |
1588 		(p_param->const_intra_pred_flag << 1) |
1589 		(p_param->lf_cross_slice_boundary_enable << 2) |
1590 		(p_param->wpp_enable << 4) |
1591 		(p_param->disable_deblk << 5) |
1592 		((p_param->beta_offset_div2 & 0xF) << 6) |
1593 		((p_param->tc_offset_div2 & 0xF) << 10) |
1594 		((p_param->chroma_cb_qp_offset & 0x1F) << 14) |
1595 		((p_param->chroma_cr_qp_offset & 0x1F) << 19) |
1596 		(p_param->transform8x8_enable << 29) |
1597 		(p_param->entropy_coding_mode << 30);
1600 	vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx);
1603 		vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp |
1604 				((p_param->intra_period & 0x7ff) << 6) |
1605 				((p_param->avc_idr_period & 0x7ff) << 17));
1608 			      p_param->decoding_refresh_type | (p_param->intra_qp << 3) |
1609 				(p_param->intra_period << 16));
1611 	reg_val = (p_param->rdo_skip << 2) |
1612 		(p_param->lambda_scaling_enable << 3) |
1614 		(p_param->intra_nx_n_enable << 8) |
1615 		(p_param->max_num_merge << 18);
1621 			      p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode);
1624 			      p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode);
1630 		(p_param->hvs_qp_enable << 2) |
1631 		(p_param->hvs_qp_scale << 4) |
1632 		((p_param->initial_rc_qp & 0x3F) << 14) |
1635 		reg_val |= (p_param->mb_level_rc_enable << 1);
1637 		reg_val |= (p_param->cu_level_rc_enable << 1);
1641 		      p_param->rc_weight_buf << 8 | p_param->rc_weight_param);
1643 	vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i |
1644 		      (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12));
1646 	vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p |
1647 		      (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) |
1648 		      (p_param->max_qp_b << 18));
1657 		      p_param->conf_win_bot << 16 | p_param->conf_win_top);
1659 		      p_param->conf_win_right << 16 | p_param->conf_win_left);
1663 			      p_param->avc_slice_arg << 16 | p_param->avc_slice_mode);
1666 			      p_param->independ_slice_mode_arg << 16 |
1667 			      p_param->independ_slice_mode);
1683 			      p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode);
1688 			      p_param->nr_intra_weight_y |
1689 			      (p_param->nr_intra_weight_cb << 5) |
1690 			      (p_param->nr_intra_weight_cr << 10) |
1691 			      (p_param->nr_inter_weight_y << 15) |
1692 			      (p_param->nr_inter_weight_cb << 20) |
1693 			      (p_param->nr_inter_weight_cr << 25));